Sense Amplifier Timing Control for Bit Line Mismatch Compensation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Volatile memory devices require continuous power supply to retain data, limiting their data processing speed, while non-volatile memory devices offer low processing speed but do not need continuous power, necessitating improvements in data processing speed and reliability.
Innovation Solution
A semiconductor device with a control circuit that adjusts the timing of bit line connections and disconnections to a sense amplifier, enabling mismatch compensation operations to improve sensing margin and offset.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If continuous power supply is provided to volatile memory devices to retain data, then data retention is maintained, but power consumption increases and data processing speed is limited
Solution Approach 1:
The sense amplifier performs mismatch compensation operations in advance before actual data reading operations. By pre-adjusting the amplifier's offset and mismatches during idle periods or before word line activation, the system ensures accurate data retrieval without requiring continuous power supply to the memory cells themselves, thus reducing overall power consumption while maintaining data retention capabilities
Solution Approach 2:
The mismatch compensation is performed periodically or at specific timing intervals rather than continuously. The control circuit activates the sense amplifier for compensation operations at predetermined times (e.g., before read operations or during idle cycles), allowing the memory device to operate in low-power states between these periodic compensation events, thereby reducing average power consumption while maintaining reliability
2Reliability
If mismatch compensation operations are performed continuously, then sensing margin and offset are improved, but data processing speed decreases
Solution Approach 1:
Mismatch compensation operations are executed in advance before actual data read operations. The control circuit performs these compensation operations during idle periods or before word line activation, ensuring that the sense amplifier is already optimized when needed for data retrieval. This preliminary action prevents compensation operations from interfering with data processing speed while maintaining sensing margin
Solution Approach 2:
The timing of mismatch compensation operations is dynamically adjusted based on operational needs. The control circuit selectively activates compensation operations only when beneficial (e.g., before read operations or during idle cycles) rather than continuously, adapting the compensation frequency to the actual data processing requirements. This dynamic approach maintains sensing margin while minimizing impact on data processing speed
3Device complexity
If bit lines are connected to the sense amplifier at the same timing, then circuit operation is simplified, but sensing accuracy decreases due to mismatch
Solution Approach 1:
The control circuit implements asymmetric timing control for connecting bit lines to the sense amplifier. Instead of simultaneous connection, the first and second bit lines are connected at different timings during mismatch compensation operations. This asymmetric approach allows the sense amplifier to accurately compensate for mismatches between differential bit lines, thereby improving sensing accuracy while the control circuit manages the timing complexity
4Reliability
If mismatch compensation operations are performed frequently, then sensing margin is improved, but power consumption increases
Solution Approach 1:
Mismatch compensation operations are performed periodically at specific intervals rather than continuously or frequently. The control circuit schedules these compensation operations during idle cycles or before data read operations, allowing the memory device to operate in low-power states between compensation events. This periodic approach maintains sensing margin improvements while significantly reducing average power consumption compared to frequent continuous compensation
Data Source
AI summary
Disclosed is a semiconductor device including a first cell mat including memory cells connected to a first bit line, a second cell mat including memory cells connected to a second bit line, a sense amplifier configured to amplify a difference in voltages between the first bit line and the second bit line, and a control circuit configured to differently adjust timing at which the first bit line and the second bit line are connected to or disconnected from the sense amplifier.