Sense Amplifier Timing Control Using Tracking Bit and Word Lines
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Solution Overview
Problem
Existing memory modules lack flexibility in adapting the pulse-width of enabling signals for sensing amplifiers, which affects data reading accuracy and is not adaptable to different memory module demands.
Innovation Solution
A memory module design that includes a pulse-width controller, tracking bit and word lines, and sensing amplifiers, allowing for adaptive pulse-width control based on the number of inputs/outputs and supply voltages, ensuring sufficient operation time for sensing amplifiers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fixed number of serially connected inverters are used to generate the enabling signal, then the pulse-width is determined by the sum of gate delays, but the pulse-width lacks flexibility and cannot adapt to different memory module demands
Solution Approach 1:
The patent replaces the fixed inverter chain with a dynamic pulse-width controller that adjusts the enabling signal duration based on real-time feedback from the tracking bit line voltage, allowing the system to adapt to different memory module configurations and demands
Solution Approach 2:
The patent implements a feedback mechanism where the pulse-width controller monitors the tracking bit line voltage and uses this information to dynamically adjust the enabling signal pulse-width, ensuring optimal sensing performance for different memory module types
2Reliability
If the pulse-width of the enabling signal is insufficient, then the sensing amplifier operation duration is insufficient, but extending the pulse-width reduces timing flexibility
Solution Approach 1:
The pulse-width controller uses feedback from the tracking bit line voltage to dynamically determine the optimal enabling signal duration, ensuring sufficient sensing time for data reading correctness while adapting to different timing requirements of various memory modules
Solution Approach 2:
The system dynamically changes the pulse-width parameter based on the detected voltage level on the tracking bit line, allowing the enabling signal duration to be optimized for each specific memory module configuration rather than using a fixed value
3Loss of time
If serially connected inverters are used to control pulse-width, then timing control is achieved, but considerable layout area is occupied
Solution Approach 1:
The patent uses a tracking bit line and tracking cell that replicate the electrical characteristics of the actual bit line and memory cell, allowing the pulse-width controller to be designed with reduced complexity and area while still achieving accurate timing control through the tracking mechanism
Data Source
AI summary
A memory module with improved timing adaptivity of sensing amplification, comprises at least one sensing amplifier, a tracking word line, a tracking bit line and a pulse-width controller. The tracking word line comprises a front node and an end node. Each said sensing amplifier is enabled/disabled when an enabling signal is activated/deactivated. The pulse-width controller is coupled to the tracking bit line, the front node and the end node. When a voltage of the tracking bit line changes to a predetermined voltage, the pulse-width controller activates the enabling signal, and causes a voltage of the front node to change. When the voltage of the front node changes, the tracking word line causes a voltage of the end node to change after a first delay time. When the voltage of the end node changes, the pulse-width controller deactivates the enabling signal after a second delay time.