DRAM Sense Amplifier Timing Control for Data Sensing Accuracy
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Solution Overview
Problem
In semiconductor integrated circuits, particularly DRAM devices, the difference in threshold voltage between PMOS and NMOS transistors in sense amplifiers leads to errors in data sensing due to premature activation of PMOS transistors over NMOS transistors, especially at high VDD conditions, causing inaccuracies in data retrieval.
Innovation Solution
The apparatus introduces a timing control unit that generates a predetermined time difference between the enable timings of driving signals for PMOS and NMOS transistors, ensuring that NMOS transistors are activated before PMOS transistors, using a structure with delayed output from PMOS drivers to stabilize data sensing operations across varying power supply voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the sense amplifier uses conventional CMOS inverters with latch structure, then the device complexity is reduced and manufacturing is easier, but threshold voltage differences between PMOS and NMOS transistors cause data sensing errors
Solution Approach 1:
The patent applies preliminary action by generating the NMOS driving signal (SAN) before the PMOS driving signal (SAP) through a controlled delay circuit. This ensures that NMOS transistors are turned on first to establish proper voltage levels before PMOS transistors are activated, preventing threshold voltage differences from causing sensing errors while maintaining the conventional CMOS inverter structure
Solution Approach 2:
The patent introduces an intermediary delay circuit between the signal generation and the CMOS inverters. This delay circuit acts as a mediator that coordinates the timing of NMOS and PMOS transistor activation, ensuring proper sequence without requiring changes to the fundamental CMOS inverter latch structure
2Power
If the semiconductor integrated circuit operates at high VDD condition, then the power consumption is reduced and performance is improved, but the time difference between NMOS and PMOS driving signals is reduced causing sensing errors
Solution Approach 1:
The patent applies dynamics by making the delay time adjustable rather than fixed. The delay circuit dynamically adapts the time difference between NMOS and PMOS driving signals based on operating conditions, particularly maintaining sufficient time separation even at high VDD conditions where transistor switching speeds increase and would otherwise reduce the effective time difference
3Ease of manufacture
If the channel lengths of MOS transistors are slightly changed during manufacturing, then the manufacturing process is simplified, but threshold voltage differences between transistors increase causing sensing errors
Solution Approach 1:
The patent applies parameter changes by modifying the timing parameters of the driving signals rather than attempting to control transistor physical parameters. By adjusting the time difference between SAN and SAP signals, the system compensates for threshold voltage variations caused by channel length variations during manufacturing, maintaining proper transistor activation sequence despite process variations
Data Source
AI summary
An apparatus includes a plurality of first driving signal driving units, and generates a first driving signal by driving an input signal, a plurality of second driving signal driving units, each of which drives an input signal and generates a second driving signal, a timing control unit that controls each of the first driving signal driving units such that a predetermined time difference is generated between an enable timing of the first driving signal and an enable timing of the second driving signal, a plurality of sense amplifier driving units, each of which generates a first driving level and a second driving level according to the first driving signal and the second driving signal, and a plurality of sense amplifiers that are provided for respective bit line pairs, and each include first type switching elements operating according to the first driving level and second type switching elements operating according to the second driving level.