Sense Amplifier Transistor Stacking for Memory Detection

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Solution Overview

Problem

Current sense amplifiers in memory circuits face challenges in accurately detecting and amplifying the states of memory cells, particularly in volatile memory systems where data needs to be frequently refreshed, and in non-volatile systems that require precise state determination across multiple levels.

Innovation Solution

A latch-based sense amplifier construction is introduced, comprising n-type and p-type transistors with specific semiconductor material pillars and activation lines, along with conductive coupling mechanisms to enhance the detection and amplification of memory cell states, allowing for improved voltage sensing and data retention.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional sense amplifiers are used in memory circuits, then the basic detection function is provided, but the accuracy of detecting and amplifying memory cell states deteriorates, particularly in volatile memory systems requiring frequent refresh and non-volatile systems requiring precise multi-level state determination

Engineering Contradiction:
Improveaccuracy of detecting and amplifying memory cell statesVSAvoiddata retention and detection reliability
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The sense amplifier is divided into multiple specialized components: a first sense amplifier for detecting first states, a second sense amplifier for detecting second states, and a third sense amplifier for detecting third states. Each sense amplifier is configured to detect specific states with optimized parameters, thereby improving the overall measurement precision and reliability of memory cell state detection without requiring a single complex amplifier to handle all states

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The sense amplifiers are configured with adjustable parameters including gain, bandwidth, and threshold voltages that can be dynamically optimized based on the specific memory cell state being detected. This dynamic configuration allows each sense amplifier to adapt its characteristics for optimal detection accuracy of different states, improving both measurement precision and reliability

Inventive Principle:
Principle #15Dynamics

2Measurement precision

If the sense amplifier construction is enhanced with multiple transistor types and material pillars, then the detection accuracy improves, but the device complexity increases

Engineering Contradiction:
Improvevoltage sensing accuracyVSAvoidtransistor and material structure complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

Multiple functionality is merged into a single sense amplifier construction by integrating n-type and p-type transistors with different semiconductor material pillars (first, second, third, and fourth pillars) within one device structure. This merging allows the sense amplifier to detect multiple voltage levels and states simultaneously, improving measurement precision while avoiding the need for separate amplifier circuits for each state

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The sense amplifier construction is designed as a universal device capable of detecting multiple states (first states, second states, and third states) with different voltage characteristics. The inclusion of diverse transistor types and material pillars enables the single device to perform multiple detection functions, thereby improving measurement precision across different memory cell states without proportionally increasing overall device complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10580464B2Sense amplifier constructions
Publication Date: 2020.03.03 MICRON TECHNOLOGY INC
  • US10580464B2 patent drawing
  • US10580464B2 patent drawing
  • US10580464B2 patent drawing

AI summary

A sense amplifier construction comprises a first n-type transistor and a second n-type transistor above the first n-type transistor. A third p-type transistor is included and a fourth p-type transistor is above the third p-type transistor. A lower voltage activation line is electrically coupled to n-type source/drain regions that are elevationally between respective gates of the first and second n-type transistors. A higher voltage activation line is electrically coupled to p-type source/drain regions that are elevationally between respective gates of the third and fourth p-type transistors.