Sense Amplifier Bit Line Voltage Compensation via Capacitive Coupling
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Solution Overview
Problem
In non-volatile memory, parasitic capacitors with large capacitance between bit lines lead to longer charge/discharge times, and conventional methods fail to set appropriate voltage levels during fast-pass-write operations, reducing efficiency.
Innovation Solution
A sense amplifier with multiple bit line drivers is used, where one bit line is set for fast-pass-write and an adjacent bit line is adjusted to compensate the voltage level through capacitive coupling, ensuring appropriate voltage levels are achieved for efficient operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional bit line driving methods are used during fast-pass-write operations, then the operation speed is maintained, but the voltage level on the bit line cannot be set appropriately due to large parasitic capacitance
Solution Approach 1:
The patent introduces an adjacent bit line as an intermediary element to compensate for voltage level issues on the FPW bit line. By adjusting the voltage on the adjacent bit line, the parasitic capacitance between bit lines is utilized to indirectly control and set the appropriate voltage level on the FPW bit line, solving the voltage precision problem without directly increasing charge/discharge time
Solution Approach 2:
The patent changes the voltage parameter of the adjacent bit line to compensate for the FPW bit line voltage. By dynamically adjusting the adjacent bit line's voltage level, the system achieves appropriate voltage setting on the FPW bit line while maintaining fast operation speed, effectively resolving the contradiction between voltage precision and charging time
2Productivity
If the voltage level on the bit line is not appropriately set during fast-pass-write operations, then the operation speed is maintained, but the efficiency of the fast-pass-write operation is reduced
Solution Approach 1:
The patent implements a feedback mechanism where the voltage level on the adjacent bit line is adjusted based on the requirements of the FPW operation. This feedback control ensures that the FPW bit line achieves the appropriate voltage level for efficient operation, thereby improving overall productivity without sacrificing voltage accuracy
Solution Approach 2:
The adjacent bit line serves as a mediator to improve FPW efficiency. By controlling the adjacent bit line's voltage, the system indirectly optimizes the FPW bit line's voltage level, ensuring efficient operation while maintaining the speed advantages of fast-pass-write mode
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively compensates the voltage on fast-pass-write bit lines, improving the efficiency of fast-pass-write operations by optimizing voltage levels and load management between bit lines.
Implementation Method 1
the bit line driver of bit line adjacent to the first bit line adjust voltage level of the adjacent bit line for compensation the voltage on the FPW bit line by capacitive coupling effect
Data Source
AI summary
A sensing amplifier includes a first bit line driver, a second bit line driver and a third bit line driver. The first bit line driver sets a first bit line for a fast-pass-write (FPW) operation. The second bit line driver sets a second bit line for a first operation rather than the FPW operation. The third bit line driver sets a third bit line for a second operation rather than the FPW operation. The first bit line is arranged between the second bit line and the third bit line, and the second bit line driver and the third bit line driver respectively adjust voltage statuses of the second bit line and the third bit line to rise a voltage level of the first bit line by a compensated level.