Sense-Circuit Memory Logic Without Sense Line Address Access
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Solution Overview
Problem
Existing semiconductor memory systems face challenges in performing logical operations efficiently, particularly in terms of power consumption and parallel processing, as they often require data transfer between processing resources and memory arrays, leading to increased chip size and power usage.
Innovation Solution
The implementation of sensing circuitry within the memory array that can perform logical operations without transferring data via a sense line address access, allowing for parallel processing and reduced power consumption by using a primary latch to sense memory cells and a secondary latch to accumulate results, thereby eliminating the need for external processing resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is transferred between processing resources and memory arrays via bus, then logical operations can be executed, but processing performance is reduced and power consumption increases
Solution Approach 1:
The patent combines the processing resources (functional units) directly with the memory array on the same chip, eliminating the need for external data transfer via bus. This integration allows processing operations to be performed locally within the memory device, significantly improving processing performance while reducing power consumption associated with data movement between separate components.
2Area of stationary object
If processing resources are implemented external to memory array, then chip size is reduced, but data access time increases
Solution Approach 1:
The patent implements processing resources (functional units capable of performing logical operations) directly within the memory device chip. This multi-functional integration allows the same chip to serve both as memory storage and as a processing unit, eliminating the time delay associated with external data access while maintaining a compact chip-scale form factor.
3Productivity
If PIM device integrates processor internal to memory, then processing performance is improved, but chip size increases
Solution Approach 1:
The patent segments the processing functionality into discrete functional units that can be selectively activated. Rather than implementing a complete processor architecture, the memory device includes specific functional units capable of performing logical operations directly on stored data. This segmentation approach improves processing performance for specific operations while minimizing the additional chip area required.
4Reliability
If data is sensed and transferred via sense line address access, then memory cells can be read, but power consumption increases
Solution Approach 1:
The patent enables the memory device to perform processing operations self-servingly within the memory array using the existing sensing infrastructure. Functional units directly access and process data from memory cells using the sense lines, eliminating the need to transfer data externally for processing. This self-service approach maintains reliable data sensing capability while significantly reducing power consumption by avoiding external data movement.
Data Source
AI summary
The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. The sensing circuitry can be configured to perform a first operation phase of a logical operation by sensing a memory cell coupled to the sense line, perform a number of intermediate operation phases of the logical operation by sensing a respective number of different memory cells coupled to the sense line, and accumulate a result of the first operation phase and the number of intermediate operation phases in a secondary latch coupled to the primary latch without performing a sense line address access.