Sense Circuit for Resistance Variable Memory Data State Sensing

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Solution Overview

Problem

Existing sensing methods for resistance variable memory cells often result in errors when determining the data state, as they may incorrectly sense the resistance state due to variations in signal responses, leading to incorrect logic states being assigned.

Innovation Solution

The implementation of a sense circuit that applies an evaluation signal to resistance variable memory cells, samples and holds signal responses, and amplifies arithmetic combinations of these responses to accurately determine the data state by analyzing voltage differences, thereby improving the accuracy of data state sensing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If simple sensing methods are used to determine data state, then device complexity is reduced, but measurement precision deteriorates due to incorrect sensing of resistance state

Engineering Contradiction:
Improvesensing circuit complexityVSAvoiddata state sensing accuracy
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The sensing process is divided into multiple discrete steps: applying first evaluation signal, applying second evaluation signal, applying third evaluation signal, sampling responses, and amplifying differences. This segmentation allows each step to be optimized independently, improving measurement precision without overwhelming complexity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Reference memory cells are introduced as intermediary elements to provide reference signals for comparison. These reference cells enable differential sensing that compensates for variations and improves accuracy without requiring direct absolute measurements

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If multiple evaluation signals are applied to improve sensing accuracy, then measurement precision improves, but loss of time increases due to additional sensing steps

Engineering Contradiction:
Improvedata state sensing accuracyVSAvoidsensing operation time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

Multiple evaluation signals are applied in a periodic sequence (first, second, and third signals at different times), allowing the system to gather multiple measurements systematically. This periodic approach enables accurate differential sensing while maintaining a structured timing regimen that optimizes speed

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The first evaluation signal is applied before the second and third signals to establish baseline measurements. This preliminary action allows subsequent measurements to be differential comparisons, reducing the time needed for full characterization while maintaining precision

Inventive Principle:
Principle #10Preliminary action

3Measurement precision

If differential sensing with multiple signals is used, then measurement precision improves, but device complexity increases due to additional circuit components

Engineering Contradiction:
Improveresistance state measurement accuracyVSAvoidsense circuit structure
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The sense circuit is designed to perform multiple functions: applying evaluation signals, sampling responses, amplifying differences, and determining data states. By making the circuit multi-functional, the patent reduces the need for separate dedicated components for each function, managing complexity while achieving high measurement precision

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS9640239B2Sense circuits, semiconductor devices, and related methods for resistance variable memory
Publication Date: 2017.05.02 MICRON TECHNOLOGY INC
  • US9640239B2 patent drawing
  • US9640239B2 patent drawing
  • US9640239B2 patent drawing

AI summary

Sense circuits, memory devices, and related methods are disclosed. A sense circuit includes sample and hold circuitry configured to sample and hold a second response voltage potential, a first response voltage potential, and a third response voltage potential responsive to an evaluation signal applied to a resistance variable memory cell. The sense circuit includes an amplifier operably coupled to the sample and hold circuitry. The amplifier is configured to amplify a difference between a sum of the first response voltage potential and the third response voltage potential, and twice the second response voltage potential. A memory device includes an evaluation signal generating circuit configured to provide the evaluation signal, an array of resistance variable memory cells, and the sense circuit. A method includes applying the evaluation signal to the resistance variable memory cell, sampling and holding the response voltage potentials, and discharging the sample and hold circuitry to the amplifier.