Sense Circuit with Two-Step Clock for Memory Cell Verification
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Solution Overview
Problem
Existing memory devices face challenges in efficiently sensing the conductive state of memory cells, particularly in 3D memory structures, due to the need for multiple verify operations and the time-consuming nature of verify tests, which can lead to increased programming time and reduced accuracy.
Innovation Solution
A sense circuit that uses a single control gate voltage to sense the threshold voltage (Vth) of a memory cell relative to two different levels, allowing for faster sensing operations by performing two strobes after increasing the sense node voltage to a peak level and using a trip point transistor with a lower Vth, enabling more accurate discharge rate variation and reduced programming time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple verify operations are performed to accurately sense memory cell states, then measurement precision is improved, but loss of time increases
Solution Approach 1:
The sensing operation is segmented into two distinct phases: a first sensing phase that evaluates the memory cell state at an intermediate voltage level, and a second sensing phase that evaluates at a final voltage level. This segmentation allows the system to quickly eliminate clearly pass/fail cases in the first phase, then perform a more precise verification only on borderline cases in the second phase, thereby maintaining high accuracy while reducing overall sensing time.
Solution Approach 2:
The first sensing operation is performed as a preliminary step before the second sensing operation. By initially sensing at the intermediate voltage level and determining a preliminary pass/fail status, the system can identify which memory cells require further verification. This preliminary action filters out memory cells that are clearly in pass or fail states, so that the time-consuming second sensing operation is only applied to uncertain cases, thus reducing total programming time while maintaining accuracy.
2Measurement precision
If a larger trip point transistor is used to improve sensing accuracy, then measurement precision is improved, but device complexity and area increase
Solution Approach 1:
The system dynamically adjusts the voltage level applied to the memory cell during sensing operations. By switching between intermediate and final voltage levels, the system can achieve accurate sensing with a smaller trip point transistor, as the dynamic voltage adjustment compensates for the reduced transistor size. This allows the trip point transistor to operate effectively across different voltage conditions without requiring excessive area.
Solution Approach 2:
The sensing operation changes the voltage parameter applied to the memory cell, transitioning from an intermediate voltage level to a final voltage level. This parameter change enables the system to achieve accurate discharge rate measurement with a smaller trip point transistor, as the varying voltage levels provide sufficient signal differentiation without requiring a large transistor area for high-precision sensing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the time required for sensing operations, allows for more accurate evaluation of memory cell states, and enables the use of a smaller trip point transistor, thereby improving the efficiency and accuracy of memory cell programming in 3D memory structures.
Implementation Method 1
increase a voltage of the capacitor which steps up a voltage of the sense node to a peak level by way of capacitive coupling
Data Source
AI summary
A sense circuit is provided in which the threshold voltage of a memory cell is sensed relative to two different levels using a single control gate voltage on the memory cell. These two levels can be lower and higher verify voltages of a data state in a programming operation, or two read levels of a read operation. A sense node is charged up to a peak level by a pre-charge voltage and by capacitive coupling. The sense node then discharges into the bit line. The sense node voltage is decreased first and second times by capacitive coupling after which first and second bits of data are output based on a level of the sense node. The first and second bits indicate a level of the sense node relative to the lower and higher verify voltages, respectively.