Sense Circuitry Single Read Hard Soft Bit Data
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Solution Overview
Problem
In solid-state data storage systems, existing decoding methods face challenges in accurately retrieving data due to error-prone memory cells, particularly in multi-level cell systems where cells can be over- or under-programmed, leading to increased error rates and reduced system performance, as they often require multiple read commands for soft bit data acquisition, which is time-consuming and costly.
Innovation Solution
The system generates both hard and soft bit data in response to a single read command, utilizing sense circuitry to perform multiple read levels and logical operations to determine bit encoding and reliability, allowing for efficient error correction without additional read commands, thereby improving decoding accuracy and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple read commands are used to acquire soft bit data, then decoding accuracy is improved, but read latency increases
Solution Approach 1:
The patent combines multiple read operations (hard read and soft read) into a single unified read command. The sense circuitry performs both hard bit data sensing and soft bit data sensing in one operation, eliminating the need for sequential read commands. This merging approach maintains high decoding accuracy while significantly reducing read latency.
Solution Approach 2:
The patent performs soft bit data sensing as a preliminary action within the same read command structure used for hard bit data. By preparing and executing soft read levels during the normal read operation without requiring additional command overhead, the system obtains reliability information in advance, improving decoding accuracy without time penalty.
2Reliability
If multiple read commands are executed for soft bit data acquisition, then error correction capability is improved, but system performance deteriorates
Solution Approach 1:
The patent merges soft bit data acquisition with the standard hard bit data read operation into a single command execution. The sense circuitry simultaneously performs hard sensing and soft sensing, consolidating what would traditionally require multiple separate operations. This maintains robust error correction capability while preserving system performance by eliminating redundant command overhead.
Solution Approach 2:
The read command structure is designed to serve multiple functions simultaneously: it performs both hard bit data retrieval and soft bit data acquisition for error correction. The sense circuitry is configured to execute multiple sensing operations (hard read levels and soft read levels) within a single command framework, making the read operation universal and multi-functional.
3Reliability
If additional read commands are used for soft bit data, then decoding reliability is improved, but overhead increases
Solution Approach 1:
The patent combines soft bit data sensing with hard bit data sensing into a single read command execution. The sense circuitry performs both types of sensing operations without requiring additional command protocols or communication overhead. This merging approach maintains high decoding reliability while minimizing the increase in operational complexity.
Solution Approach 2:
The sense circuitry is designed to automatically perform both hard and soft sensing operations as part of its standard read function. The system self-services by integrating soft bit data acquisition into the existing read command infrastructure, eliminating the need for separate error correction read commands and reducing overall system overhead.
Data Source
AI summary
An apparatus includes memory cells programmed to one of a plurality of data states, wherein the memory cells are configured such that the plurality of data states comprise an error-prone data state. Sense circuitry of the apparatus is configured to sense first memory cells programmed to the error-prone data state, determine a bit encoding for the first memory cells, sense other memory cells programmed to other data states, and determine a bit encoding for the other memory cells. A communication circuit of the apparatus is configured to communicate the bit encoding for the other memory cells, the bit encoding for the first memory cells, and an indication that the first memory cells are programmed to the error-prone data state, in response to a single read command from a controller.