Sense Counter-Pulse Circuit for Wider Memory Read Windows
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Solution Overview
Problem
Non-volatile memories face read errors due to parasitic capacitance across state-programmable memory elements, which reduces the switching charge and narrows the read window, leading to potential errors in determining the programmed state.
Innovation Solution
Implement a dual-sided sense amplifier configuration with a counter-pulse generation circuit that applies a compensation voltage to counteract the parasitic capacitance by using a complementary bit line to offset the voltage loss during a read operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a read voltage is applied to one side of the state-programmable memory element, then the state can be read out, but the parasitic capacitance reduces the switching charge and narrows the read window
Solution Approach 1:
A counter-pulse generation circuit is introduced as an intermediary component that produces a compensation signal. This counter-pulse circuit acts as a mediator between the read operation and the parasitic capacitance effect, generating a voltage that actively compensates for the charge loss caused by parasitic capacitance, thereby maintaining a wide read window and preventing read errors
Solution Approach 2:
The system applies a counter-pulse voltage in advance or simultaneously with the read voltage to preemptively counteract the harmful effect of parasitic capacitance. By generating a compensation voltage that opposes the charge loss, the system prevents the narrowing of the read window before it can occur, ensuring reliable reading operation
2Device complexity
If the parasitic capacitance is present across the memory element, then the memory structure is simplified, but the switching charge is reduced leading to read errors
Solution Approach 1:
The counter-pulse generation circuit serves as an intermediary that addresses the reliability issue without requiring fundamental changes to the memory structure. This additional circuit component compensates for the parasitic capacitance effect, allowing the simplified memory structure to maintain high read operation reliability through active charge compensation
3Device complexity
If the switching charge is reduced due to parasitic capacitance coupling, then the read window narrows, but the memory cell structure remains simple
Solution Approach 1:
The counter-pulse generation circuit applies a preliminary compensating voltage that prevents the read window from narrowing. By generating a voltage signal that opposes the parasitic capacitance coupling effect before it can reduce the switching charge, the system maintains a wide read window while keeping the memory cell structure simple
Solution Approach 2:
The system dynamically adjusts the voltage parameter by introducing a counter-pulse voltage that changes in response to the read operation. This parameter change (voltage compensation) counteracts the effect of parasitic capacitance, maintaining optimal read window width without complicating the physical memory cell structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The compensation voltage technique maintains a wide read window and improves the reliability of the sense amplifier by ensuring a larger difference in developed voltages for '0' and '1' states, enhancing the read operation's accuracy and efficiency.
Implementation Method 1
a parasitical capacitance may exist across the state-programmable memory element that may reduce switching charge
Implementation Method 2
the read voltage that is applied to one side of the state-programmable memory element (e.g., at the plate line) may couple across the parasitic capacitance
Data Source
AI summary
Disclosed herein are devices, methods, and systems for reading a programmed state of a memory element. The method includes setting a bit line to which the memory element is connected to a first voltage and developing to the bit line a compensation voltage different from the first voltage. The method also includes developing a modified sensing voltage to the bit line defined by the compensation voltage and a sensing voltage developed from the memory element and determining the programmed state based on the modified sensing voltage. A complementary memory element may be used to develop the compensation voltage by discharging a complementary plate line, to which the second memory element is connected, to charge a complementary bit line to which the second memory element is connected and by connecting the bit line to the complementary bit line to develop the compensation voltage to the bit line.