Differential Sense Flip-Flop with Switchable Discharge Paths
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Solution Overview
Problem
Sequential state elements, such as master slave flip flops, are slow and energy inefficient, while differential sense flip flops are prone to noise due to floating nodes, making them less robust and vulnerable to charge injection/ejection.
Innovation Solution
The Kulkarni Vrudhula flip flop incorporates a differential sense amplifier with switchable discharge paths to prevent output nodes from floating, increasing robustness to noise and reducing vulnerability to conductance variations, while maintaining energy efficiency and improving operating speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If differential sense flip flop is used to improve speed and energy efficiency, then operating speed and energy efficiency are improved, but floating nodes make the circuit more vulnerable to noise and charge injection
Solution Approach 1:
The patent introduces an equalizer transistor as an intermediary element that actively compensates for conductance mismatches between differential branches. This mediator transistor monitors and corrects voltage imbalances at the floating nodes, preventing noise vulnerability while maintaining the speed and energy efficiency benefits of the differential sense flip-flop architecture.
Solution Approach 2:
The patent dynamically adjusts the conductance parameter of the equalizer transistor to compensate for process variations and mismatches. By changing the operating parameters of the equalizer transistor based on detected imbalances, the circuit maintains robustness against noise while preserving the high-speed operation of the differential sense flip-flop.
2Reliability
If equalizer transistor is added to prevent floating nodes, then robustness to noise is improved, but conductance mismatches cause vulnerability to evaluation errors
Solution Approach 1:
The patent implements a feedback mechanism where the equalizer transistor is controlled by a signal that detects voltage imbalances between the differential branches. This feedback loop continuously monitors and corrects conductance mismatches, compensating for manufacturing variations and ensuring reliable operation despite process tolerances.
Solution Approach 2:
The equalizer transistor automatically detects and corrects its own operational imbalances through the feedback mechanism. The circuit self-regulates by having the equalizer transistor adjust its conductance in response to detected mismatches, eliminating the need for external calibration or manual adjustment.
3Reliability
If master slave flip flop is used to improve reliability, then robustness and noise immunity are improved, but speed and energy efficiency deteriorate
Solution Approach 1:
The patent segments the flip-flop operation into distinct phases (evaluation phase and hold phase) controlled by clock signals. During the evaluation phase, the differential sense amplifier rapidly captures input changes, while during the hold phase, the latch maintains the output state. This segmentation enables both high-speed operation during evaluation and stable noise immunity during the hold phase.
Solution Approach 2:
The patent employs periodic clock signals to alternately enable the evaluation and hold phases of the flip-flop. This periodic action allows the circuit to rapidly evaluate inputs during active phases while maintaining stable outputs during inactive phases, achieving both high speed and high reliability through time-division operation.
Data Source
AI summary
A differential sense flip flop (DSFF) that is named the Kulkarni Vrudhula flip flop (KVFF) is disclosed. In one embodiment, the DSFF includes a differential sense amplifier and an SR latch. The differential sense amplifier includes a first amplifier branch having a first output node, a second amplifier branch having a second, a first switchable discharge path, and a second switchable discharge path. The first switchable discharge path is closed to discharge the first output node when first output node is being discharged by the first amplifier branch and the second switchable discharge path is closed to discharge the second output node when second output node is being discharged by the second amplifier branch. This prevents the output nodes from floating and increases the reliability and robustness of the DSFF.