Sense-Latch Memory Logic for In-Array Compute Without Address Access
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Solution Overview
Problem
Existing semiconductor memory systems face challenges in reducing power consumption and increasing parallel processing capabilities when performing logical operations, particularly in processor-in-memory (PIM) devices, which often require significant power to transfer data between processing resources and memory arrays, and may have limitations due to mismatched pitch rules between memory cells and logic gates.
Innovation Solution
The implementation of sensing circuitry that performs logical operations directly within the memory array, using a primary latch and secondary latch to accumulate results without requiring sense line address access, allowing for parallel execution of operations like AND, OR, NAND, and XOR without transferring data via buses or I/O lines, and forming compute components on pitch with memory cells to conform to specific feature sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If processing resources are implemented external to the memory array, then device complexity is reduced, but data transfer power consumption increases and processing speed decreases
Solution Approach 1:
The patent merges processing resources with the memory array by implementing functional units directly within the memory structure. Sense amplifiers are configured to perform logical operations (AND, OR, NAND, NOR, XOR, XNOR) on data stored in memory cells, eliminating the need for separate external processing units and reducing data transfer requirements.
Solution Approach 2:
The sense amplifiers are designed to perform multiple functions: traditional data sensing/readout operations and logical computation operations. This multi-functionality allows the same circuitry to handle both memory access and processing tasks, reducing overall device complexity while improving energy efficiency.
2Productivity
If processing resources are implemented internal to the memory array, then processing speed increases, but chip area increases
Solution Approach 1:
Processing functions are merged with memory structures, allowing computation to occur in-place during memory operations. This eliminates the need for separate processing units and their associated data pathways, thereby improving processing speed without proportionally increasing chip area.
Solution Approach 2:
The patent utilizes the vertical dimension of the memory array structure by implementing functional units that operate on data already present in the memory cells. This allows processing to occur in the same physical space as storage, rather than requiring additional horizontal chip area for separate processing units.
3Use of energy by moving object
If data is transferred via buses or I/O lines for processing, then device complexity is reduced, but power consumption increases and processing efficiency decreases
Solution Approach 1:
The patent extracts the essential processing function from external processing resources and implements it directly within the memory array. This allows logical operations to be performed on data in-place, eliminating the need for data transfer via buses or I/O lines and significantly reducing power consumption.
4Productivity
If sense line address access is required for each operation, then manufacturing precision is maintained, but processing speed decreases
Solution Approach 1:
The patent implements preliminary action by pre-configuring the sense amplifiers with the necessary logic functions and maintaining data in the memory cells in a state ready for computation. This allows multiple logical operations to be performed without requiring repeated address access cycles, thereby improving processing speed while maintaining manufacturing precision through standardized circuit design.
Data Source
AI summary
The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. The sensing circuitry can be configured to perform a first operation phase of a logical operation by sensing a memory cell coupled to the sense line, perform a number of intermediate operation phases of the logical operation by sensing a respective number of different memory cells coupled to the sense line, and accumulate a result of the first operation phase and the number of intermediate operation phases in a secondary latch coupled to the primary latch without performing a sense line address access.