Sense Amplifier Latch Reuse for Reset Read Disturb Mitigation
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Solution Overview
Problem
Threshold-type memory devices face reliability issues due to read disturb on resets (RDR) that cause cumulative threshold voltage degradation, leading to memory operation failures, exacerbated by short minimum read-to-read durations and error correction code errors.
Innovation Solution
Incorporating retry circuitry that reuses data stored in a sense amplifier latch without re-engaging the memory array for consecutive read operations, thereby reducing threshold voltage degradation and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional read operations are performed frequently with short minimum read-to-read durations, then memory access speed and productivity are improved, but cumulative threshold voltage degradation occurs leading to reliability deterioration
Solution Approach 1:
The patent applies preliminary action by detecting RDR susceptibility before performing read operations. The system identifies memory cells that are prone to read disturb effects in advance, and takes preventive measures by avoiding repeated reads of susceptible cells or by adjusting read parameters beforehand, thus preventing threshold voltage degradation before it occurs
Solution Approach 2:
The patent implements feedback mechanisms by monitoring memory cell states and read operation outcomes. The system uses feedback from previous read operations to identify patterns of RDR susceptibility, adjusts subsequent read operations based on this information, and dynamically modifies read strategies to mitigate cumulative threshold voltage degradation while maintaining access speed
2Reliability
If error correction code operations are performed to mitigate read disturb effects, then memory reliability is improved, but power consumption and operational complexity increase
Solution Approach 1:
The patent applies partial action by selectively applying error correction code operations only to memory cells or regions that exhibit RDR susceptibility, rather than performing ECC on all memory operations. This selective approach maintains reliability for vulnerable cells while reducing overall power consumption and operational overhead
Solution Approach 2:
The patent changes operational parameters by adjusting read voltage levels, timing parameters, or access patterns based on detected RDR susceptibility. These parameter modifications reduce the need for intensive error correction operations, thereby lowering power consumption while maintaining reliability
Data Source
AI summary
Methods and systems include memory devices having multiple memory cells configured to store data. The memory devices also include control circuitry including retry circuitry. The retry circuitry is configured to receive a read command having a target address. The retry circuitry is also configured to determine that the target address of the data stored in the memory cells is to be reused from a previous read operation. Additionally, the retry circuitry is configured to cause reading of the data from a sense amplifier latch from the previous read operation by reusing the target address. Specifically, reusing the target address includes bypassing rereading the data into the sense amplifier latch from the memory cells for a current read operation.