Sense Node Voltage Control for Multi-Level Cell Memory
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Solution Overview
Problem
In semiconductor memory devices, the increasing integration and capacity lead to narrower threshold voltage gaps between multi-level cells, making it challenging to prevent threshold voltage changes due to capacitive coupling from neighboring cells during programming operations, which can result in erroneous data reading and storage.
Innovation Solution
A semiconductor memory device and method that involves storing data in a page buffer, adjusting read voltages based on threshold voltage changes, and performing reprogram operations using specific read and verification voltages to correct threshold voltage shifts, ensuring accurate data reading and storage by distinguishing between different threshold voltage distributions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level cells are used to increase integration and capacity, then storage density is improved, but threshold voltage gaps between cells become narrower making it difficult to prevent threshold voltage changes due to capacitive coupling
Solution Approach 1:
The patent applies preliminary action by performing a read operation before the reprogram operation to detect threshold voltage changes caused by capacitive coupling. The read voltage is adjusted based on the data state of neighboring cells, and this preliminary detection allows the system to prepare appropriate compensation actions before the actual reprogram occurs, preventing erroneous programming due to threshold voltage shifts
Solution Approach 2:
The patent implements parameter changes by dynamically adjusting the read voltage applied to memory cells during the reprogram operation. The read voltage is modified based on the detected threshold voltage distribution and data states of neighboring cells, allowing the system to compensate for capacitive coupling effects and maintain accurate threshold voltage measurement during the reprogram process
2Productivity
If threshold voltage gaps are narrowed to increase integration, then chip capacity is improved, but capacitive coupling from neighboring cells causes threshold voltage changes leading to erroneous data reading
Solution Approach 1:
The patent implements feedback by using the result of the preliminary read operation to determine the appropriate read voltage for the reprogram operation. The system reads the data state of neighboring cells, detects threshold voltage changes, and uses this feedback information to adjust the read voltage accordingly, creating a closed-loop control mechanism that compensates for capacitive coupling effects and maintains measurement precision
Solution Approach 2:
The patent applies dynamics by making the read voltage adaptive and variable rather than fixed. The read voltage is dynamically adjusted based on the real-time data states of neighboring cells and the detected threshold voltage distribution, allowing the system to respond to changing conditions during the reprogram operation and maintain accurate data reading despite narrow threshold voltage gaps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances data reliability by correcting threshold voltage shifts caused by capacitive coupling, maintaining a sufficient read margin and preventing erroneous data reading, thereby improving the accuracy and integrity of data storage in multi-level cell memory devices.
Implementation Method 1
prevention of the threshold voltages of memory cells from being changed due to the capacitive coupling resulting from the threshold voltages of neighboring memory cells during a program operation
Data Source
AI summary
A semiconductor memory device comprises memory blocks having a plurality of memory cells coupled to a plurality of bit lines, a first latch group coupled to a sense node and configured to store data to be programmed into memory cells, where the memory cells are coupled to the bit lines and the sense node is coupled to at least one of the bit lines, a second latch group coupled to the sense node and configured to receive data of the first latch group, and a sense node voltage control circuit configured to control a voltage of the sense node according to data stored in the first latch group.