Sense Terminal Lead Layout for Lower On-Resistance MOSFET Packages
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Solution Overview
Problem
In semiconductor devices used in applications with large current flow, such as 3-phase inverters, the on-resistance significantly affects performance, and existing configurations like the 'TO package' face challenges in reducing on-resistance due to the bending of wires connecting the source terminal and source terminal lead, leading to increased resistance and performance degradation.
Innovation Solution
The semiconductor device configuration includes arranging the source terminal lead between the gate terminal lead and the Kelvin terminal lead in a plan view, allowing for a straight wire connection that reduces on-resistance and parasitic inductance, thereby improving performance by minimizing wire bending and optimizing current path length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the source terminal lead is arranged in a conventional position in the TO package, then the package structure is simple and easy to manufacture, but the wire connecting the source terminal and source terminal lead must be bent, increasing on-resistance and parasitic inductance
Solution Approach 1:
The patent changes the spatial arrangement of the source terminal lead from a conventional side-position to a position between the gate terminal lead and Kelvin terminal lead in plan view. This dimensional repositioning allows the wire to connect the source terminal and source terminal lead in a straight line, eliminating bends and reducing both on-resistance and parasitic inductance while maintaining package manufacturability
2Area of stationary object
If the wire connecting source terminal and source terminal lead is bent to accommodate conventional lead arrangement, then the package layout is compact, but the on-resistance and parasitic inductance increase significantly
Solution Approach 1:
The patent introduces asymmetric positioning of the source terminal lead relative to other terminals. By placing the source terminal lead between the gate terminal lead and Kelvin terminal lead rather than symmetrically arranging all leads, the design creates an optimized current path that minimizes wire length and eliminates bends, thereby reducing on-resistance and parasitic inductance for high-current applications
Data Source
AI summary
In order to reduce on-resistance in a semiconductor device to be used for high current applications, the semiconductor device includes a source terminal lead located between a gate terminal lead and a Kelvin terminal lead in plan view and electrically connected with a source terminal via a plurality of wires.