Sense Transistor Wafer Testing for Power Current Measurement
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Solution Overview
Problem
Wafer testing of power transistors is challenging due to the inability of fine probe needles to carry significant amounts of power, making it difficult to accurately measure current properties.
Innovation Solution
Using a sense transistor constructed from the same epitaxial stack as the power transistor, which is pre-conditioned by alternately turning on and off while allowing the source terminal of the power transistor to float, and heating the wafer to simulate operating conditions, allowing for accurate measurement of current properties before dicing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If fine probe needles are used to contact the power transistor during wafer testing, then the probing capability and measurement precision are improved, but the ability to carry significant amounts of power deteriorates
Solution Approach 1:
The invention separates the measurement function from the power handling function by using two different transistors: a sense transistor for measurement and a power transistor for power handling. The sense transistor is used exclusively for measuring current properties with fine probe needles, while the power transistor handles significant power without affecting the measurement capability.
Solution Approach 2:
The sense transistor acts as an intermediary device that allows indirect measurement of the power transistor's current properties. By measuring the sense transistor's current properties and using the known relationship between the two transistors, the invention enables accurate measurement of power transistor characteristics without requiring the probe needles to carry significant power.
2Productivity
If wafer testing is performed before dicing, then the productivity and manufacturing efficiency are improved, but the ability to accurately measure current properties of power transistors deteriorates due to probe limitations
Solution Approach 1:
The invention enables wafer-level testing of power transistors by segmenting the measurement function into a separate sense transistor that can be accurately measured with fine probe needles. This allows productive wafer testing before dicing while maintaining measurement accuracy through the sense transistor proxy.
3Measurement precision
If the sense transistor is pre-conditioned by alternately turning on and off, then the measurement accuracy of the power transistor is improved, but the testing time and process complexity increase
Solution Approach 1:
The sense transistor undergoes pre-conditioning by alternately turning on and off before measurement to simulate actual operating conditions. This preliminary action ensures that the sense transistor's characteristics accurately reflect the power transistor's behavior during normal operation, thereby improving measurement accuracy.
4Measurement precision
If the wafer is heated to simulate operating conditions, then the measurement accuracy under real operating conditions is improved, but the device complexity and energy consumption increase
Solution Approach 1:
The wafer is heated to change the temperature parameter and simulate actual operating conditions. This allows measurement of current properties at temperatures representative of real-world operation, improving the accuracy and relevance of the test results.
Data Source
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AI summary
Wafer testing of a power transistor for a current property of the power transistor. Wafer testing of a power transistor is performed by using a sense transistor constructed using the same epitaxial stack as was used to construct the power transistor. The current property of the sense transistor is then measured (320), and the current property of the power transistor can be determined from that measurement (330). Furthermore, the sense transistor is pre-conditioned prior to the measurement by alternately turning on and off the sense transistor multiple cycles while allowing a source terminal of the power transistor to float (310). This simulates operating conditions of the power transistor, thereby allowing for measurement of the current property of the power transistor as it would likely be in operation (330).