Sensing Circuit With NAND-Controlled Load PMOS
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Solution Overview
Problem
As memory devices become smaller, process variations increase, making it difficult to accurately read data from resistance-based memory elements, such as magnetic tunnel junctions, due to variations in output resistance and sensing margins.
Innovation Solution
A sensing circuit that includes a NAND circuit to control the gate voltage of a load PMOS transistor, utilizing a degeneration PMOS and a clamp transistor to enhance output resistance and sensing margin, while also incorporating a boost PMOS transistor to improve sensing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If memory devices are scaled down to achieve smaller size, then device miniaturization is achieved, but process variations increase making accurate data reading difficult
Solution Approach 1:
The patent implements a feedback mechanism where the sense amplifier continuously monitors the voltage difference between the memory cell and reference cell, and dynamically adjusts the current through the load PMOS transistor. This feedback loop compensates for process variations by automatically balancing the sensing current, thereby maintaining accurate data reading despite device scaling-induced variations.
Solution Approach 2:
The patent dynamically changes the operating parameters of the sense amplifier, specifically adjusting the gate voltage of the load PMOS transistor based on the detected voltage difference. By varying the current parameter in response to process variations, the circuit maintains optimal sensing performance across different manufacturing conditions and scaled device dimensions.
2Device complexity
If a simple sense amplifier circuit is used, then device complexity is low, but output resistance and sensing margin are insufficient
Solution Approach 1:
The patent transforms the static load resistor into a dynamic load PMOS transistor whose gate voltage can be actively controlled. This dynamic element allows the circuit to adapt its output resistance and current driving capability based on the sensing requirements, thereby improving sensing margin without requiring a completely complex circuit architecture.
Solution Approach 2:
The patent performs preliminary precharging of the bit line and reference line before the actual sensing operation. By pre-establishing the voltage levels and preparing the circuit state in advance, the sense amplifier achieves better sensing margin and reliability without adding excessive complexity to the core sensing circuitry.
3Speed
If precharging current is high, then bit line charging speed is fast, but current through memory element during sensing is reduced
Solution Approach 1:
The patent employs periodic action by separating the operation into distinct phases: a precharging phase where high current is applied to quickly charge the bit line, followed by a sensing phase where the circuit transitions to a lower current state for accurate measurement. This temporal separation allows the circuit to achieve both fast charging speed and adequate sensing current by using different current levels at different times.
Data Source
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AI summary
A circuit includes a degeneration p-channel metal - oxide - semiconductor (PMOS) transistor (102), a load PMOS transistor (104), and a clamp transistor (110) configured to clamp a voltage applied to a resistance based memory element (112) during a sensing operation. A gate of the load PMOS transistor is controlled by an output of a not- AND (NAND) circuit (106).