Sensing Circuitry Logical Operations Memory Array Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional processor-in-memory (PIM) devices face challenges with increased chip size and high power consumption when performing logical operations, especially when data needs to be transferred between processing resources and memory arrays, and the circuitry often does not conform to the pitch rules of memory arrays, affecting memory density.
Innovation Solution
The implementation of sensing circuitry within the memory array that includes primary and secondary latches, allowing for the performance of logical operations without transferring data via a bus, and the ability to perform compute functions like add, subtract, multiply, and CAM operations directly within the memory array, reducing the need for external processing and minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If processor-in-memory (PIM) devices are implemented with external processing resources, then processing capability is improved, but chip size increases
Solution Approach 1:
The patent merges the processing resources directly into the memory array by implementing sense amplifiers that can perform logical operations (AND, OR, NOT, NAND, NOR, XOR) on data stored in memory cells. This integration eliminates the need for separate external processing units, thereby improving processing capability while avoiding the chip size increase that would result from adding external processors.
Solution Approach 2:
The sense amplifiers are designed to serve multiple functions: they not only read data from memory cells but also perform various logical operations and compute functions (add, subtract, multiply, CAM operations). This multi-functionality allows the same circuitry to handle both memory access and processing tasks, improving overall system productivity without requiring additional dedicated processing components that would increase chip size.
2Productivity
If data is transferred between processing resources and memory arrays via bus, then processing capability is improved, but power consumption increases
Solution Approach 1:
The patent extracts the data transfer step entirely by performing logical operations directly on the data while it remains stored in the memory array. The sense amplifiers operate on data in place, eliminating the need to transfer data via bus between separate processing resources and memory arrays, thereby significantly reducing power consumption associated with data movement.
Solution Approach 2:
The memory array becomes self-sufficient by enabling its own sense amplifiers to perform computational operations on stored data without requiring external processing resources. This self-service capability allows the memory system to execute logical operations internally, avoiding the power-intensive data transfer that would occur with external processors.
3Productivity
If compute circuitry does not conform to memory array pitch rules, then processing capability is improved, but memory density decreases
Solution Approach 1:
The patent implements compute circuitry (sense amplifiers with logical operation capability) at specific locations within the memory array structure, specifically at the column decode region where sense lines intersect with memory cell columns. This localized integration allows processing functions to be added without disrupting the overall memory array pitch and layout, thereby maintaining memory density while enabling enhanced processing capability.
Data Source
AI summary
The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array of memory cells. The sensing circuitry includes a primary latch and a secondary latch. The primary latch is coupled to a pair of complementary sense lines and selectively coupled to a pair of adjacent complementary sense lines. The secondary latch is selectively coupled to the primary latch. The primary latch and secondary latch are configured to shift a data value between the pair of adjacent complementary sense lines and the primary latch. The primary latch and secondary latch are configured to shift the data value from the pair of adjacent complementary sense lines without activating a row line.