Sensing Die Encapsulation With Hollow Region for Precise Layer Alignment
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing integrated fan-out packages due to manufacturing complexities and alignment issues during the fabrication of semiconductor packages, particularly in forming precise alignment between successive layers without affecting the circuitry layout.
Innovation Solution
A method involving the use of patterned passivation layers, sacrificial material layers, and grooving processes to create semiconductor dies with alignment marks, followed by encapsulation with a roughed surface having a hollow region to facilitate precise alignment and patterning, using dummy TIVs for alignment control and reducing surface roughness through controlled etching and encapsulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If repeated reductions in minimum feature size are used to improve integration density, then more components can be integrated into a given area, but manufacturing complexity and alignment issues increase
Solution Approach 1:
The patent divides the semiconductor package into distinct functional layers including an encapsulation layer, a sensing component layer, and a substrate layer. This segmentation allows each layer to be optimized and manufactured separately, then assembled together, thereby maintaining integration density while reducing overall manufacturing complexity.
Solution Approach 2:
The patent transitions from planar integration to three-dimensional stacking by placing the sensing component within a hollow region of the encapsulation layer. This vertical arrangement enables higher integration density without proportionally increasing manufacturing complexity, as each layer can be processed independently before assembly.
2Manufacturing precision
If precise alignment between successive layers is achieved through complex fabrication processes, then alignment precision improves, but manufacturing complexity increases
Solution Approach 1:
The patent incorporates alignment marks during the encapsulation layer formation process, before the sensing component is placed. These pre-formed alignment marks simplify subsequent alignment operations by providing reference features that guide the positioning of the sensing component, thereby achieving precise alignment without complex real-time adjustment mechanisms.
Solution Approach 2:
The patent uses alignment marks as intermediary reference features that mediate the alignment between the encapsulation layer and the sensing component. These marks serve as a common reference system that simplifies the alignment process by providing visible, stable features that can be easily detected and used for positioning, reducing the complexity of direct component-to-component alignment.
3Ease of manufacture
If the encapsulation layer has a roughed surface to facilitate certain manufacturing processes, then ease of manufacture improves, but surface roughness increases which may affect subsequent patterning
Solution Approach 1:
The patent applies different surface characteristics to different regions of the encapsulation layer. The outer surface maintains a roughed texture to facilitate manufacturing processes such as molding or bonding, while the inner surface facing the hollow region is kept smooth to enable precise patterning and alignment of the sensing component. This local differentiation allows both manufacturing ease and precision requirements to be satisfied simultaneously.
Data Source
AI summary
A manufacturing method of a semiconductor package includes: laterally covering a sensing die with an encapsulant, where the encapsulant includes a top surface and a rounded inner edge connected to the top surface, and a top surface of the sensing die is lower than the rounded inner edge of the encapsulant and is smoother than the top surface of the encapsulant; and forming a redistribution structure on the top surface of the encapsulant and the top surface of the sensing die.