Memory Sensing Latch Trip-Level Trimming Under PVT Variation
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Solution Overview
Problem
Process voltage temperature (PVT) variations in PMOS and NMOS transistors cause variations in the trip level of sensing latches in memory devices, hindering the securing of a required sensing margin, especially for low-power operations.
Innovation Solution
Incorporation of a trim transistor circuit into the sensing latch circuit to adjust the trip level based on a trim voltage, with automatic determination using a sample sensing latch circuit during a calibration procedure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a sensing latch circuit is used for data sensing, then data sensing capability is provided, but PVT variations cause trip level variation which hinders securing required sensing margin
Solution Approach 1:
The patent applies parameter changes by introducing a trim voltage that adjusts the trip level of the sensing latch circuit. The trim voltage modifies the operating parameters of the sensing circuit to compensate for PVT variations, thereby stabilizing the trip level and ensuring reliable data sensing across different process, voltage, and temperature conditions.
Solution Approach 2:
The patent implements feedback through a calibration procedure that automatically determines the appropriate trim voltage. The system senses the actual trip level behavior and adjusts the trim voltage accordingly to achieve the desired trip level, creating a closed-loop control mechanism that maintains sensing margin under varying conditions.
2Reliability
If trim transistor circuit is added to adjust trip level, then sensing margin is secured, but device complexity increases
Solution Approach 1:
The patent uses a trim transistor circuit as an intermediary element between the power supply and the sensing latch circuit. This intermediary component allows adjustment of the trip level through a control voltage without fundamentally changing the core sensing latch structure, thereby adding minimal complexity while achieving the desired reliability improvement.
Solution Approach 2:
Instead of redesigning the entire sensing latch circuit, the patent achieves improved reliability by changing a single parameter - the trip level - through the addition of trim transistors controlled by a trim voltage. This targeted parameter adjustment minimizes the increase in device complexity while effectively securing the sensing margin.
Data Source
AI summary
A memory device for adjusting a trip level and an operating method thereof are provided. The memory device includes a cell string including memory cells, and a page buffer connected to the cell string through a bit line and configured to sense data of a selected memory cell of the memory cells through a sensing latch circuit, where the sensing latch circuit includes a sensing latch including a first inverter and a second inverter, and a trim transistor circuit electrically connected to a p-type metal oxide semiconductor (PMOS) transistor of the first inverter and configured to adjust a trip level of the sensing latch based on a trim voltage.