Sensing Margin Expanding Scheme for Memory Access Time
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Solution Overview
Problem
Conventional memory technologies face challenges in achieving low power, high speed, and high density, with sensing margin time limiting access time, especially under low supply voltage conditions, resulting in slow margin development and longer access times.
Innovation Solution
A sensing margin expanding scheme for memory that employs a sense amplifier, two capacitors, and common switches, along with a controller, to store and double the voltage difference between the bit line and reference voltage, thereby enhancing the sensing margin and reducing access time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional read scheme is used, then device complexity is low, but sensing margin develops slowly resulting in longer access time
Solution Approach 1:
The patent applies preliminary action by pre-charging capacitors C1 and C2 to store voltage differences before the actual sensing operation. The controller first charges C1 with voltage difference between bit line and reference voltage, then charges C2 with voltage difference between bit line and ground. This preliminary charging action prepares the sensing margin expansion circuitry in advance, enabling faster sensing without requiring complex real-time computation during the read operation.
Solution Approach 2:
The patent uses capacitors C1 and C2 as intermediary elements to store and transfer voltage differences. These capacitors act as mediators between the bit line voltage and the sense amplifier input, converting the voltage difference into stored charge that can be read out faster. The capacitors serve as energy intermediaries that bridge the gap between the slow conventional read scheme and the faster required sensing operation.
2Use of energy by moving object
If low supply voltage is used, then power consumption is reduced, but sense amplifier needs more read margin against PVT variation
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the voltage margins presented to the sense amplifier through capacitor charging operations. Under low supply voltage conditions, the controller charges C1 and C2 to create enhanced voltage differences that compensate for reduced supply voltage. This changes the effective voltage parameter at the sense amplifier input, maintaining reliable sensing margin despite low power consumption conditions.
Solution Approach 2:
The patent implements beforehand cushioning by pre-charging capacitors C1 and C2 to store voltage differences that will compensate for PVT variations during sensing. The controller performs these charging operations in advance, creating a cushion of stored energy that protects the sensing operation against future voltage drops or variations. This prior cushioning ensures reliable sensing margin is maintained even under low supply voltage conditions.
3Measurement precision
If bit line capacitance is coupled to sensing amplifier, then sensing operation is enabled, but bit line voltage drops over time reducing sensing margin
Solution Approach 1:
The patent applies preliminary action by pre-charging capacitors C1 and C2 to store voltage differences before the sensing operation begins. The controller first performs charging operations where C1 stores voltage difference between bit line and reference voltage, and C2 stores voltage difference between bit line and ground. This preliminary action captures the voltage information before the bit line voltage drops, preserving the sensing margin for the actual detection operation.
Solution Approach 2:
The patent uses capacitors C1 and C2 as intermediary storage elements that decouple the sensing operation from the bit line voltage decay. Instead of directly sensing the decaying bit line voltage, the system uses these capacitors as intermediaries to store the voltage differences at optimal times, then releases this stored information to the sense amplifier. This intermediary approach preserves measurement precision despite the time-dependent voltage drop.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This scheme effectively doubles the sensing margin, resulting in approximately twice the access time improvement and faster read access times across a wide supply voltage range.
Implementation Method 1
A first terminal of the first capacitor is coupled to at least a bit line of the memory. A second terminal of the second capacitor is coupled to a pre-sense amplifier. A first terminal of the second capacitor is coupled to a reference voltage. A second terminal of the first capacitor is coupled to the pre-sense amplifier.
Data Source
AI summary
A sensing margin expanding scheme for a memory and a method therefor is disclosed. A first terminal of a first capacitor is coupled to a bit line. A first terminal of a second capacitor is coupled to a reference voltage. In a first phase, the controller controls a first common switch and a second common switch to store the voltage difference between the bit line and the reference voltage to the first capacitor and the second capacitor. In a second phase, controlling the first common switch and the second common switch to open the first terminal of the first capacitor and the second terminal of the second capacitor and open the second terminal of the first capacitor and the first terminal of the second capacitor, and then coupling the second terminal of the first capacitor and the second terminal of the second capacitor to a common voltage.