Semiconductor Sensing Pad Structure to Suppress Gate Pad Peeling
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Solution Overview
Problem
The adhesion between the barrier metal layer and the interlayer dielectric film in semiconductor devices is weak, leading to peeling issues when stress is applied, which can result in the removal of the gate pad and affect the device's performance.
Innovation Solution
The introduction of a tungsten portion within the through hole in the interlayer dielectric film, which enhances the adhesion between the barrier metal layer and the interlayer dielectric film, reducing the area of the interface where peeling can occur.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a barrier metal layer is formed on the interlayer dielectric film, then electrical connectivity is improved, but adhesion between the barrier metal layer and interlayer dielectric film deteriorates
Solution Approach 1:
A tungsten plug is introduced as an intermediary element between the barrier metal layer and the interlayer dielectric film. The tungsten plug fills a through-hole in the interlayer dielectric film and provides a mechanical anchor that enhances adhesion. The barrier metal layer is formed over the tungsten plug, creating a three-layer structure where the tungsten plug acts as a mediator that improves both electrical connectivity and adhesion strength simultaneously.
2Ease of operation
If stress is applied to the semiconductor device, then device operation is enabled, but peeling of the barrier metal layer occurs
Solution Approach 1:
The tungsten plug is formed beforehand in the interlayer dielectric film to create a mechanical anchor structure. This pre-formed plug cushions against the peeling force that occurs when stress is applied during device operation. The plug's presence before stress application prevents the barrier metal layer from peeling away from the dielectric film, maintaining layer integrity during subsequent operational stress.
Data Source
AI summary
A semiconductor device including a semiconductor substrate, the semiconductor device including: a sensing portion that is provided on the semiconductor substrate and that is configured to detect predetermined physical information; a sensing pad portion that is provided above an upper surface of the semiconductor substrate and that is connected to the sensing portion; a gate runner which is provided above the upper surface of the semiconductor substrate and to which a gate potential is applied; and one or more separated conductive portions in which each separated conductive portion is provided between the sensing pad portion and the semiconductor substrate and that is separated from the gate runner.