Microarchitectural Sensitive Tag Flow for Side-Channel Attack Mitigation
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Solution Overview
Problem
Side-channel attacks, such as Portsmash, can reveal sensitive information by measuring timing differences in processor execution, leading to over-protection issues where most instructions become marked as sensitive, causing performance saturation and inefficiency.
Innovation Solution
Implementing a microarchitectural mechanism to dynamically designate instructions as sensitive, using additional bits in instructions or system control registers to selectively protect sensitive instructions, and employing thread-level granularity to partition pipeline resources, allowing only same-thread instructions to execute during sensitive instruction cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all instructions are marked as sensitive to prevent side-channel attacks, then security is improved, but performance deteriorates due to saturation and over-protection
Solution Approach 1:
The patent applies local quality by marking only specific instructions as sensitive rather than all instructions. Each instruction can have an individual sensitive bit that determines whether it requires protected execution. This selective approach ensures security for critical instructions while maintaining normal performance for non-sensitive instructions, resolving the contradiction between comprehensive security and overall performance.
Solution Approach 2:
The patent segments the instruction stream into sensitive and non-sensitive portions using per-instruction sensitive bits. This segmentation allows the processor to apply different execution policies to different instructions - protected execution for sensitive instructions and normal execution for non-sensitive ones. The segmentation prevents performance saturation while maintaining security where needed.
2Reliability
If thread-level granularity is used to partition pipeline resources, then security against side-channel attacks is improved, but device complexity increases
Solution Approach 1:
The patent implements dynamic thread identification and partitioning mechanisms that adaptively manage pipeline resources based on the sensitive bit status of executing instructions. The processor dynamically switches between protected and unprotected execution modes, and between single-thread and multi-thread operation, based on real-time instruction characteristics. This dynamic approach provides security when needed while maintaining efficiency and managing complexity through adaptive behavior rather than static over-engineering.
Data Source
AI summary
Described herein are systems and methods for microarchitectural sensitive tag flow. For example, some methods include detecting dependence of data stored in a second data storage circuitry on the first instruction, where the first instruction will output a value to be stored in the second data storage circuitry, and wherein the second data storage circuitry is associated with a third tag indicating whether the second data storage circuitry has been designated as storing sensitive data; responsive to the dependence of data stored in the second data storage circuitry on the first instruction, checking whether the second tag indicates a sensitive instruction; and, responsive to the second tag indicating a sensitive instruction, updating the third tag to indicate that data stored in the second data storage circuitry has been designated as sensitive.