Sensor-Array Processor Time-Domain Signal Processing

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Solution Overview

Problem

Existing sensor array systems face challenges in efficiently processing signals in 3D environments due to noise and interference, particularly in applications like automatic speech recognition, where high reverberation and multiple interference sources limit performance, and current frequency domain processing methods incur significant latency and computational costs.

Innovation Solution

An integrated sensor-array processor that operates in the time-domain with a sensor transform engine, spatial filter engine, noise reduction filter engine, and inverse transform engine, allowing for non-uniform frequency spacing and frame rates, which reduces latency and computational costs while enhancing signal processing efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If frequency domain processing is used to improve signal filtering performance, then filtering performance is improved, but latency increases significantly

Engineering Contradiction:
Improvefiltering performanceVSAvoidlatency
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The system dynamically switches between time-domain and frequency-domain processing modes based on signal characteristics and performance requirements. The processor can adaptively select the optimal processing domain for different operating conditions, combining the low latency of time-domain processing with the high filtering performance of frequency-domain processing.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The invention changes the processing domain parameter from fixed frequency-domain to variable between time-domain and frequency-domain. By transforming the signal processing approach and using overlap-add methods with optimized block sizes, the system achieves frequency-domain filtering performance with reduced latency compared to traditional FFT-based approaches.

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If frequency domain processing is used to improve signal filtering performance, then filtering performance is improved, but computational cost increases

Engineering Contradiction:
Improvefiltering performanceVSAvoidcomputational cost
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The signal processing is segmented into manageable blocks that are processed independently using overlap-add methods. This segmentation allows the system to apply frequency-domain filtering to smaller data segments, reducing the overall computational burden while maintaining filtering performance through systematic recombination of processed segments.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention extracts and processes only the essential frequency components needed for filtering, rather than performing complete frequency domain transformation of entire signals. By selecting specific frequency bins and processing only necessary data segments, the system reduces computational cost while preserving critical filtering performance.

Inventive Principle:
Principle #2Taking out (Extraction)

3Loss of time

If faster FFT frame rate is used to reduce latency, then latency is reduced, but computation cost increases 4×

Engineering Contradiction:
ImprovelatencyVSAvoidcomputation cost
Core Design Contradiction:
Loss of timeVSProductivity

Solution Approach 1:

The system performs partial frequency domain processing by computing only the necessary frequency bins required for filtering, rather than performing complete FFT transformations. This partial action approach achieves the latency reduction goal while avoiding the exponential computation cost increase that would result from processing all frequency components at higher rates.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The overlap-add method enables continuous processing of signal segments with smooth transitions between blocks. This continuity allows the system to maintain low latency by processing overlapping segments in parallel or pipelined fashion, improving computational efficiency compared to discrete non-overlapping block processing.

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS10049685B2Integrated sensor-array processor
Publication Date: 2018.08.14 AAWARE INC
  • US10049685B2 patent drawing
  • US10049685B2 patent drawing
  • US10049685B2 patent drawing

AI summary

An integrated sensor-array processor and method includes sensor array time-domain input ports to receive sensor signals from time-domain sensors. A sensor transform engine (STE) creates sensor transform data from the sensor signals and applies sensor calibration adjustments. Transducer time-domain input ports receive time-domain transducer signals, and a transducer output transform engine (TTE) generates transducer output transform data from the transducer signals. A spatial filter engine (SFE) applies suppression coefficients to the sensor transform data, to suppress target signals received from noise locations and/or amplification locations. A blocking filter engine (BFE) applies subtraction coefficients to the sensor transform data, to subtract the target signals from the sensor transform data. A noise reduction filter engine (NRE) subtracts noise signals from the BFE output. An inverse transform engine (ITE) generates time-domain data from the NRE output.