Semiconductor Sensor Back Flow Prevention for Etch-Stop
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Solution Overview
Problem
Conventional semiconductor physical quantity sensors, such as pressure sensors, are affected by parasitic transistors during the electrochemical etch-stop process, leading to defects and inefficient etching, especially when integrating sophisticated and downsized designs with CMOS circuits where there is no room for n+-type buried diffused layers.
Innovation Solution
Incorporating a MOSFET as a back flow prevention element between the diaphragm and conductive pattern, which applies a predetermined voltage to the well layer, preventing parasitic transistor activation and allowing for precise etching without the need for additional manufacturing steps or buried diffused layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a diode is formed to prevent short-circuit in the electrochemical etch-stop process, then short-circuit prevention is improved, but a parasitic transistor is created that causes current leakage and etching defects
Solution Approach 1:
The patent extracts and removes the parasitic transistor structure by eliminating the p-type substrate connection that creates the three-terminal transistor configuration. The diode structure is modified to connect only between the anode and cathode without forming a parasitic path to the substrate, thereby taking out the harmful parasitic element while preserving the desired short-circuit prevention function.
Solution Approach 2:
The patent converts the potentially harmful parasitic transistor effect into a beneficial controlled diode operation. By carefully designing the diode connection to avoid substrate contact, the current path is controlled to flow only through the intended diode junction, transforming what would be a parasitic leakage path into a controlled forward-biased diode connection that aids in voltage application during etching.
2Reliability
If an n+-type buried diffused layer is added as a carrier stopper to prevent parasitic transistor influence, then parasitic transistor effects are reduced, but the manufacturing process complexity and number of steps increase
Solution Approach 1:
The patent takes out and eliminates the need for the n+-type buried diffused layer by redesigning the diode connection architecture. Instead of adding a carrier stopper layer, the solution removes the structural configuration that creates the parasitic transistor in the first place, thereby simplifying the manufacturing process while achieving the same reliability improvement.
Solution Approach 2:
Instead of adding a buried diffused layer to suppress the parasitic transistor (the conventional approach), the patent inverts the strategy by removing the p-type substrate connection that creates the parasitic transistor structure. This inverted approach achieves parasitic suppression through structural elimination rather than additive suppression layers.
3Adaptability or versatility
If the sensor is downsized and integrated with CMOS circuits, then integration capability is improved, but there is no room for n+-type buried diffused layers to prevent parasitic transistors
Solution Approach 1:
The patent extracts and removes the dependency on n+-type buried diffused layers by redesigning the diode connection to avoid substrate contact. This extraction of the parasitic transistor formation mechanism enables downsized sensor design with CMOS integration while maintaining reliability, as the solution does not require additional space-consuming buried layers.
Solution Approach 2:
The patent merges the diode structure directly with the sensor element and CMOS circuit interface, eliminating the need for separate parasitic suppression structures. The diode connection is integrated into the existing sensor architecture, allowing compact downsized design while inherently preventing parasitic transistor formation through the modified connection topology.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration ensures that the semiconductor physical quantity sensor operates without parasitic transistor influence, enabling precise pressure detection and simplifying the manufacturing process by eliminating the need for extra layers, thus enhancing the sensor's reliability and integration capabilities.
Implementation Method 1
an anisotropic etching is performed by an electrochemical etch-stop technique as an etching process to form the diaphragm
Implementation Method 2
an oxide film is formed on a surface of the semiconductor substrate by anode oxidation, and therefore the etching process is stopped
Implementation Method 3
The back flow prevention element is arranged on a first electrical wiring, which provides a passage for applying a predetermined voltage to the well layer from an external circuit. The back flow prevention element turns on, based on a voltage applied to a gate electrode.
Data Source
AI summary
A semiconductor physical quantity sensor includes (i) a semiconductor substrate having a first conductive type, (ii) a diaphragm portion disposed in the semiconductor substrate, (iii) a sensing portion disposed in the diaphragm portion, (iv) a well layer having a second conductive type, and (v) a back flow prevention element. The well layer is disposed in a surface portion of the semiconductor substrate, and corresponds to the diaphragm portion. The back flow prevention element is provided by a MOSFET, a JFET, a MESFET, or a HEMT. The back flow prevention element includes two second conductive diffused portions and a gate electrode. The back flow prevention element is arranged on a first electrical wiring, which provides a passage for applying a predetermined voltage to the well layer from an external circuit. The back flow prevention element turns on based on a voltage applied to the gate electrode.