Sensor Array Bias Distribution Using Local Current Mirrors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing bias distribution systems for large arrays of sensors in smartphones and tablets require a large number of interconnect lines, consuming routing resources and valuable area, especially for touch and fingerprint sensing which demands a large array of sensors, and are prone to variations in supply voltage and ground, affecting bias current stability.
Innovation Solution
A bias generation circuit using a main PMOS transistor, a main NMOS transistor, and a main resistor serially coupled, with a local bias replica in each sensor, mirroring currents to reduce interconnect lines to two, minimizing the impact of supply voltage and ground fluctuations, and optimizing transistor and resistor sizes to improve mismatch and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a large number of interconnect lines are used to distribute bias current or voltage to support a large array of sensors, then the bias distribution can cover more sensors, but the routing resources are consumed and valuable area is taken
Solution Approach 1:
The bias distribution system is segmented into multiple bias generation circuits, each serving a specific group of sensors. Instead of using a single centralized bias source requiring numerous interconnect lines to reach every sensor, the system divides the sensor array into segments, with each segment having its own local bias generation circuit. This segmentation reduces the total number of interconnect lines needed while maintaining coverage for a large number of sensors.
2Quantity of substance
If a large number of interconnect lines are used to distribute bias current or voltage to support a large array of sensors, then the bias distribution can cover more sensors, but routing resources are consumed
Solution Approach 1:
The system segments the bias distribution function across multiple independent bias generation circuits, reducing the complexity of routing. Each segment handles a subset of sensors locally, eliminating the need for complex global routing infrastructure that would be required to connect a centralized bias source to all sensors.
Solution Approach 2:
Each bias generation circuit is designed as a universal module that can serve multiple sensors within its segment. The same circuit topology and component configuration are reused across different segments, standardizing the routing requirements and reducing overall routing complexity through multi-functionality.
3Reliability
If bias voltage or current is derived from a source with low variation such as a bandgap reference, then good sensitivity is achieved, but the bias distribution requires more interconnect lines
Solution Approach 1:
The system segments the bias generation function so that each segment has its own local bias generation circuit with a bandgap reference. This ensures that each segment maintains high bias stability independently, while avoiding the need for extensive interconnect lines that would be required to distribute a single centralized bias source to all segments.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution significantly reduces the number of interconnect lines needed, stabilizes bias currents, and minimizes power consumption and area usage, while maintaining reliable bias distribution across a large array of sensors.
Implementation Method 1
mirroring currents to reduce interconnect lines to two
Data Source
AI summary
In certain aspects, a bias generation circuit comprises a bias voltage generator. The bias voltage generator has a main NMOS transistor having a drain and a gate of the main NMOS transistor both coupled to a first terminal, a main resistor having a first main resistor terminal and a second main resistor terminal, wherein the first main resistor terminal couples to a source of the main NMOS transistor; and a main PMOS transistor having a source of the main PMOS transistor coupled to the second main resistor terminal and a drain and a gate of the main PMOS transistor both coupled to a second terminal, wherein the second terminal couples to a main ground. The bias generation circuit further comprises an array of sensors coupled to the first terminal and the second terminal.