Sensor Array Bias Circuit With Local Mirroring to Cut Routing Lines
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Solution Overview
Problem
The existing bias distribution systems for large arrays of sensors in smartphones and tablets require a large number of interconnect lines, consuming significant routing resources and area, and are prone to variations in supply voltage and ground, which affects the reliability and stability of bias current or voltage, especially in touch and fingerprint sensing applications.
Innovation Solution
A bias generation circuit with a main PMOS and NMOS transistor and resistor configuration generates two bias voltages, which are mirrored locally at each sensor, reducing the need for numerous interconnect lines and minimizing the impact of supply voltage and ground fluctuations through differential bias structures and optimized resistor and transistor sizing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a large number of interconnect lines are used to distribute bias current or voltage to support a large amount of sensors, then the bias distribution can cover more sensors, but the routing resources are consumed and valuable area is taken
Solution Approach 1:
The bias distribution system is segmented into a main bias generation circuit and multiple local bias replicas distributed across the sensor array. Each local replica independently generates bias currents from a single bias voltage, eliminating the need for numerous individual bias distribution lines to each sensor.
Solution Approach 2:
The invention uses local bias replicas that copy the bias generation functionality from the main circuit to distributed locations. Each replica is a simplified version that can generate appropriate bias currents locally, replacing the need for direct connection to the central bias source.
2Ease of manufacture
If supply voltage and ground are used for bias distribution, then the implementation is simple, but variations in supply voltage and ground affect the reliability and stability of bias current or voltage
Solution Approach 1:
The local bias replicas use feedback mechanisms through their transistor configurations to automatically compensate for supply voltage and ground variations. The feedback ensures that bias currents remain stable despite fluctuations in the power supply, maintaining reliability without complex implementation.
3Quantity of substance
If a large array of sensors is implemented, then the sensing coverage is increased, but the number of bias distribution lines increases significantly
Solution Approach 1:
The bias distribution system is divided into independent local units (bias replicas) that can be distributed throughout the large sensor array. This segmentation allows each unit to operate independently with minimal interconnect requirements, supporting large sensor arrays without proportionally increasing distribution complexity.
Solution Approach 2:
The local bias replicas serve multiple functions: they generate bias currents, compensate for supply variations, and can be replicated across the entire sensor array using the same simple circuit design. This universality allows the system to scale to large sensor arrays without increasing the complexity of individual distribution units.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the number of interconnect lines required, enhances the stability of bias currents, and conserves area by using only two interconnect lines for bias distribution, while maintaining reliable bias voltage delivery across the sensor array.
Implementation Method 1
A bias generation circuit with a main PMOS and NMOS transistor and resistor configuration generates two bias voltages, which are mirrored locally at each sensor
Data Source
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AI summary
In certain aspects, a bias generation circuit comprises a bias voltage generator. The bias voltage generator has a main NMOS transistor having a drain and a gate of the main NMOS transistor both coupled to a first terminal, a main resistor having a first main resistor terminal and a second main resistor terminal, wherein the first main resistor terminal couples to a source of the main NMOS transistor; and a main PMOS transistor having a source of the main PMOS transistor coupled to the second main resistor terminal and a drain and a gate of the main PMOS transistor both coupled to a second terminal, wherein the second terminal couples to a main ground. The bias generation circuit further comprises an array of sensors coupled to the first terminal and the second terminal.