Sensor Chip Bump Connection for Noise Reduction

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Solution Overview

Problem

Sensors with passive and active chip connections via wire bonding are prone to electromagnetic noise, leading to a reduction in the signal-to-noise ratio due to longer distances between the chips, which affects the quality of the electrical signal communication.

Innovation Solution

A sensor design where the active and passive chips are connected via a bump, with the passive chip having a thicker portion on a substrate, allowing for a shorter connection distance and using thermosetting adhesive for stable positioning, and metal-containing gold for low resistance connections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If wire bonding is used to connect active chip and passive chip terminals, then the terminals can be connected, but the distance between chips becomes long which allows electromagnetic noise to interfere with the electrical signal

Engineering Contradiction:
Improvesignal-to-noise ratioVSAvoiddistance between chips
Core Design Contradiction:
ReliabilityVSLength of stationary object

Solution Approach 1:

The patent merges the active chip and passive chip into a single integrated structure where the passive chip is formed as a substrate with through-holes, and the active chip is mounted directly on this substrate. This integration eliminates the need for separate wire bonding connections and reduces the distance between chips, thereby minimizing electromagnetic noise interference and improving the signal-to-noise ratio.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent transitions from planar terminal connections to three-dimensional vertical connections through through-holes in the passive chip substrate. The electrical connections are established via bumps that extend vertically through the substrate thickness, allowing terminals to be positioned on opposite sides of the substrate and significantly reducing the horizontal distance between chips while maintaining electrical connectivity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Ease of manufacture

If terminals are arranged to face each other for wire bonding, then wire bonding work is facilitated, but the wire length is restricted and noise is likely to be added to the electrical signal

Engineering Contradiction:
Improvewire bonding workabilityVSAvoidelectromagnetic noise
Core Design Contradiction:
Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The patent replaces the mechanical wire bonding process with a direct bump-to-bump connection system. Instead of using flexible wires that are mechanically bonded between terminals, the invention uses rigid bumps that are directly connected through the substrate thickness, eliminating the mechanical wire bonding step while achieving even better electrical connection quality and noise immunity.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent moves the connection path from a two-dimensional planar arrangement to a three-dimensional vertical arrangement. Terminals are positioned on opposite sides of the substrate and connected through vertical bumps passing through the substrate thickness, which significantly shortens the connection path length compared to wire bonding while maintaining ease of manufacturing through standardized bump formation processes.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Ease of manufacture

If the passive chip has uniform thickness, then manufacturing is simplified, but the design flexibility for optimizing terminal positioning and connection distance is reduced

Engineering Contradiction:
Improvechip manufacturing simplicityVSAvoidterminal positioning flexibility
Core Design Contradiction:
Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The patent applies local quality variation by creating through-holes only in specific regions of the passive chip substrate where terminal connections are needed, rather than uniformly throughout the entire chip. This allows the substrate to maintain its overall simple structure while providing localized complexity only where required for electrical connections, optimizing both manufacturing simplicity and design flexibility.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent segments the passive chip substrate into distinct functional regions: areas with through-holes for electrical connections and areas without. This segmentation allows independent optimization of connection pathways while maintaining the overall structural integrity and manufacturing simplicity of the chip. The through-holes are positioned strategically to enable short bump connections without requiring complex processing of the entire substrate.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration reduces electromagnetic noise interference, maintains high-quality connections, and prevents signal ratio degradation by minimizing the distance between active and passive chips, ensuring reliable signal communication.

Implementation Method 1

the passive chip terminal and the active chip terminal are connected via a bump

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Implementation Method 2

each of the active chip and the passive chip is placed on the substrate via a thermosetting adhesive

Methodology Applied
Scientific EffectAdhesion: Adhesive

Data Source

PatentUS9255940B2Sensor and method for manufacturing sensor
Publication Date: 2016.02.09 SEIKO EPSON CORP
  • US9255940B2 patent drawing
  • US9255940B2 patent drawing
  • US9255940B2 patent drawing

AI summary

A sensor includes: a substrate on which an active chip including a semiconductor circuit is disposed; and a passive chip including an acceleration sensor, and a thick portion and a thin portion, the thick portion being disposed on the substrate so as to be in contact therewith. An active chip terminal is disposed on the active chip. A passive chip terminal is disposed on the passive chip at the thin portion. The passive chip terminal and the active chip terminal face each other and are connected via a bump.