Sensor Chip Eutectic Bonding for Ultra-Thin Semiconductor Packaging
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Solution Overview
Problem
Current semiconductor packaging methods, such as COB and flip-chip, face challenges in achieving ultra-thin packaging due to complexity, high energy consumption, and high costs, with issues like stray light interference and the need for high-temperature, high-pressure processes.
Innovation Solution
A method involving nano low-melting-point metal materials with a melting point gradient is used to form a eutectic bond between a substrate and a sensor chip, utilizing a bonding layer on each component, aligned and compressed under controlled temperature (30° C. to 180° C.) and pressure (1 MPa to 8 MPa) conditions, with ultrasonic treatment to facilitate bonding without the need for wires or balls.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If COB packaging method is used with wire bonding, then electrical connection is achieved, but package thickness increases due to high wire arcs and stray light interference occurs
Solution Approach 1:
The patent removes the wire bonding process entirely from the packaging structure. Instead of using wires to connect pads, the invention uses direct pad-to-pad contact through the same plane bonding technique, eliminating the source of stray light interference and reducing package thickness.
Solution Approach 2:
The patent inverts the traditional bonding approach by bonding chips in the same plane rather than stacking them vertically. This same-plane bonding allows direct electrical contact without requiring wire arcs to bridge gaps, thereby reducing package thickness while maintaining electrical connection reliability.
2Length of stationary object
If flip-chip process is used with spherical bumps, then package thickness is reduced, but process complexity and cost increase due to high temperature, high pressure, and ultrasonic processes
Solution Approach 1:
The patent changes the bonding parameters from high temperature, high pressure, and ultrasonic conditions to low temperature, low pressure, and vibration conditions. This parameter transformation simplifies the manufacturing process while achieving the same thickness reduction goal through same-plane bonding without spherical bumps.
Solution Approach 2:
The patent eliminates the need for expensive spherical bumps (gold balls) by using direct pad-to-pad bonding. This removes the requirement for complex bump preparation processes and expensive materials, significantly reducing manufacturing cost while maintaining the thin package structure.
3Reliability
If spherical bumps are prepared for flip-chip bonding, then electrical connection is achieved, but process time and energy consumption increase
Solution Approach 1:
The patent performs preliminary alignment of pads in the same plane before bonding, eliminating the need for subsequent spherical bump preparation and alignment steps. This preliminary positioning of pads directly on the substrate surface streamlines the process and reduces overall manufacturing time.
Solution Approach 2:
The patent removes the spherical bump preparation step entirely from the manufacturing process. By using direct pad-to-pad bonding, the time-consuming processes of bump formation, alignment, and attachment are eliminated, significantly reducing total process time while maintaining electrical connection reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables ultra-thin semiconductor packaging with reduced thickness, lower energy consumption, and lower production costs, simplifying the process while maintaining reliability and avoiding stray light interference.
Implementation Method 1
treating the composite structure at a temperature of 30° C. to 180° C., under a pressure of 1 MPa to 8 MPa, and with an ultrasonic of 10 kHz to 30 kHz for a period of time to form the first bonding layer and the second bonding layer into a eutectic
Implementation Method 2
treating the composite structure at a temperature of 30° C. to 180° C., under a pressure of 1 MPa to 8 MPa, and with an ultrasonic of 10 kHz to 30 kHz for a period of time to form the first bonding layer and the second bonding layer into a eutectic
Data Source
AI summary
A semiconductor package and a method of manufacturing the same, and an imaging apparatus are provided. The method includes preparing a substrate having a first connection region and a sensor chip having a second connection region. A first bonding layer including multi-layer nano low-melting-point metal materials with different melting point gradients is provided on the first connection region. A second bonding layer including multi-layer nano low-melting-point metal materials with different melting point gradients is provided on the second connection region. The substrate and the sensor chip are overlapped to align and tightly compress the first and second bonding layers, to obtain a composite structure. The composite structure is treated at a temperature of 30 to 180° C., under a pressure of 1 to 8 MPa, and with an ultrasonic of 10 to 30 kHz to form the first and second bonding layers into a eutectic.