Semiconductor Pressure Sensor Chip Signal Feedback and Protection Layers
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Solution Overview
Problem
Existing semiconductor-based pressure sensors face challenges in achieving reproducible sensitivity for minute pressure differences due to difficulties in manufacturing thin membrane thicknesses and require additional cover layers that can affect mechanical properties and signal hysteresis.
Innovation Solution
A semiconductor-based pressure sensor chip design that incorporates a bridge circuit with signal feedback to the gate electrodes of transistors, amplifying the initial bridge detuning caused by mechanical stress, without the need for additional transistors, and includes signal preprocessing to condition and compensate for nonlinearities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a pressure sensor chip is thinned to enable wafer-level hermetic sealing, then packaging hermeticity is improved, but the chip becomes susceptible to breakage from handling stress and dicing saw blades
Solution Approach 1:
A dicing protection layer is applied to the backside of the pressure sensor chip before the thinning process. This protective layer prevents breakage during handling and dicing operations, allowing the chip to be thinned to the required thickness for hermetic sealing while maintaining mechanical integrity during manufacturing.
Solution Approach 2:
The protection concept is segmented into multiple functional layers: a dicing protection layer applied before thinning to prevent mechanical damage, and an etch protection layer applied after thinning to protect specific areas during subsequent etching processes. This segmented approach addresses different mechanical and chemical challenges at different manufacturing stages.
2Strength
If protection layers are added to prevent breakage, then chip strength is improved, but the number of manufacturing steps increases
Solution Approach 1:
The dicing protection layer and etch protection layer are combined into a single continuous protective structure on the chip backside. This merged approach provides both mechanical protection during dicing and chemical protection during etching, reducing the total number of separate protection steps compared to applying multiple discrete protective layers at different stages.
3Reliability
If the chip is thinned for wafer-level sealing, then packaging hermeticity is improved, but manufacturing precision requirements increase due to stress control
Solution Approach 1:
The intrinsic stress of the thin film is modified by adjusting the thickness of the etch protection layer. By changing this geometric parameter, the overall stress state of the thinned chip can be controlled to remain within acceptable limits, enabling precise thickness control while maintaining structural integrity and achieving hermetic sealing.
Data Source
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AI summary
The invention relates to an arrangement for a semiconductor-based pressure sensor chip comprising: piezoresistive elements (8) which are formed with an electrically doped channel (6) in a layer arrangement (3) in the region of a pressure membrane (4) of a semiconductor substrate (1); an electrically conductive cover layer (12) which is formed in the layer arrangement (3) and is electrically insulated from the piezoresistive elements (8) by means of an insulating layer (9); a bridge circuit of transistors, each of which are formed with one of the piezoresistive elements (8), wherein gate electrodes (10) of the transistors are arranged in electrically doped layer regions in the electrically conductive cover layer (12), said layer regions being formed separately from one another; and a signal feedback using which an output signal present at the output of the bridge circuit is fed back in a signal-amplifying manner to one or more of the gate electrodes (10). The invention also relates to a pressure sensor chip.