Chemical Sensor Array Clock Phasing for Low-Noise ISFET Readout
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Solution Overview
Problem
Noise within the circuitry of chemical sensor arrays, particularly in ion-sensitive field effect transistors (ISFETs), becomes a significant issue as sensors detect minute changes and low concentrations of chemical species, leading to propagating errors and data inaccuracies.
Innovation Solution
A system that generates a set of clock signals with staggered edges, where each clock signal is synchronous with a primary clock signal but asynchronous with others, to prevent simultaneous current pull from the power supply, reducing in-rush current and switcher noise, and allowing for easier noise compensation during data processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If sensors detect minute changes and low concentrations of chemical species, then measurement precision is improved, but noise within circuitry increases causing propagating errors
Solution Approach 1:
The patent segments the clock signals into multiple asynchronous phases distributed to different switchers. This segmentation prevents simultaneous current draw from the power supply, reducing power supply noise and ground bounce that would otherwise interfere with sensitive sensor measurements of minute chemical changes.
Solution Approach 2:
The patent employs periodic clock signals with staggered phases distributed to multiple switchers. This periodic action with time-separated current draw reduces instantaneous power demand variations and associated electromagnetic interference, thereby decreasing circuitry noise while maintaining measurement precision for low-concentration chemical species.
2Productivity
If multiple switchers draw power simultaneously from the power supply, then productivity is improved, but in-rush current and switcher noise increase
Solution Approach 1:
The patent uses periodic clock signals with staggered phases to control multiple switchers. This ensures that switchers operate in a distributed periodic manner rather than simultaneously, reducing in-rush current while maintaining overall power transfer efficiency and productivity.
Solution Approach 2:
The patent implements preliminary timing offsets in the clock signal distribution to each switcher. This preliminary action schedules power draw events to be time-separated, preventing simultaneous in-rush current while ensuring all switchers eventually complete their power transfer tasks, maintaining productivity.
3Productivity
If multiple switchers draw power simultaneously from the power supply, then productivity is improved, but power variance increases
Solution Approach 1:
The patent segments the power draw timing across multiple switchers using phased clock signals. This segmentation distributes the total power demand over time, reducing instantaneous power variance while maintaining overall power transfer efficiency and productivity.
Solution Approach 2:
The patent employs periodic staggered clock signals to distribute power draw events across multiple switchers. This periodic distribution smooths out power demand variations, stabilizing power draw from the power supply while ensuring all switchers complete their operations efficiently.
Data Source
AI summary
A system including a power supply and a clock circuitry to generate a plurality of clock signals. Each clock signal is synchronous with a primary clock signal. First, second, and third clock signals of the plurality of clock signals are asynchronous to each other. The system further includes a plurality of switches. Each switch of the plurality of switches is communicatively coupled to the power supply and the clock circuitry. A first switch of the plurality of switches receives the first clock signal, a second switch of the plurality of switches receives the second clock signal, and a third switch of the plurality of switches receives the third clock signal.