Chemical Sensor Array Clock Phasing for Low-Noise Power Switching

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Solution Overview

Problem

Noise within the circuitry of chemical sensor arrays, particularly in ion-sensitive field effect transistors (ISFETs), becomes a significant issue as sensors detect minute changes and low concentrations of chemical species, leading to propagating errors and data inaccuracies.

Innovation Solution

A system that generates a set of clock signals with staggered edges, where each clock signal is synchronous with a primary clock signal but asynchronous with others, to prevent simultaneous current pull from the power supply, reducing in-rush current and switcher noise, and allowing for easier noise compensation during data processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If multiple switchers are operated simultaneously to power sensor array components, then power delivery efficiency is improved, but noise and in-rush current increase

Engineering Contradiction:
Improvepower delivery efficiencyVSAvoidnoise and in-rush current
Core Design Contradiction:
Use of energy by moving objectVSObject-generated harmful factors

Solution Approach 1:

The patent implements periodic action by using a clock circuit to generate multiple clock signals that sequentially activate different switchers in alternating phases. This periodic switching ensures that while multiple switchers operate to maintain power delivery efficiency, they do so in a staggered manner that prevents simultaneous in-rush current spikes and reduces electromagnetic noise interference in the sensor array readings.

Inventive Principle:
Principle #19Periodic action

2Power

If clock signals to switchers are synchronous, then power transfer efficiency is improved, but noise interference with sensor readings increases

Engineering Contradiction:
Improvepower transfer efficiencyVSAvoidnoise interference
Core Design Contradiction:
PowerVSObject-generated harmful factors

Solution Approach 1:

The patent applies asymmetry by generating clock signals with different phase relationships - each clock signal is asynchronous with respect to others while remaining synchronous to a primary clock. This asymmetric phasing arrangement allows power transfer to occur efficiently through coordinated switching, while the phase differences ensure that noise from different switchers does not constructively interfere with sensor readings at the same time.

Inventive Principle:
Principle #4Asymmetry

3Productivity

If high power is supplied to switchers for rapid data acquisition, then productivity is improved, but noise and power variance increase

Engineering Contradiction:
Improvedata acquisition speedVSAvoidnoise and power variance
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The patent segments the power delivery system into multiple independently controlled switchers, each powered by its own clock signal. This segmentation allows the system to maintain high overall power delivery for rapid data acquisition across the sensor array, while individual switchers can be controlled to operate in phases, reducing peak noise and power variance that would occur if all switchers operated at maximum power simultaneously.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS8786331B2System for reducing noise in a chemical sensor array
Publication Date: 2014.07.22 LIFE TECHNOLOGIES CORP
  • US8786331B2 patent drawing
  • US8786331B2 patent drawing
  • US8786331B2 patent drawing

AI summary

A system including a power supply and a clock circuitry to generate a plurality of clock signals. Each clock signal is synchronous with a primary clock signal. First, second, and third clock signals of the plurality of clock signals are asynchronous to each other. The system further includes a plurality of switches. Each switch of the plurality of switches is communicatively coupled to the power supply and the clock circuitry. A first switch of the plurality of switches receives the first clock signal, a second switch of the plurality of switches receives the second clock signal, and a third switch of the plurality of switches receives the third clock signal.