Sensor Clock Synchronization for Mobile Energy Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Modern mobile devices face energy inefficiencies due to misalignment of sensor and processor clocks, leading to data sample loss and redundancy when polling sensors, exacerbated by poor clock accuracy in sensors with ±15% deviation over temperature ranges.
Innovation Solution
A method for synchronizing sensor clocks by correcting them at specific intervals to align with processor clocks, ensuring accurate data transfer and reducing unnecessary wake-ups, thereby conserving energy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the processor polls sensors at their sampling frequencies to collect all data samples, then data completeness is improved, but energy consumption increases due to frequent wake-ups and potential misalignment causing redundant polling
Solution Approach 1:
The patent implements a feedback mechanism where the processor receives clock accuracy information from sensors and uses this feedback to dynamically adjust polling intervals. The processor calculates optimal polling intervals based on the feedback regarding clock deviation, thereby collecting complete data samples while minimizing unnecessary wake-ups and reducing energy consumption.
Solution Approach 2:
The patent makes the polling interval dynamic rather than fixed. The polling interval is continuously adjusted based on the actual clock accuracy feedback from each sensor. This dynamic adaptation allows the system to optimize between data completeness and energy consumption by polling more frequently when clock accuracy is poor and less frequently when clock accuracy is good.
2Adaptability or versatility
If the processor uses asynchronous data transfer with interrupt signals, then data transfer flexibility is improved, but energy efficiency deteriorates due to frequent processor wake-ups for each sensor notification
Solution Approach 1:
The patent merges multiple data transfer approaches by combining elements of both asynchronous and synchronous methods. The processor uses interrupt signals for initial data availability notification but then transitions to periodic polling at optimized intervals. This hybrid approach maintains the flexibility of asynchronous transfer while improving energy efficiency by consolidating multiple potential wake-ups into scheduled polling cycles.
3Adaptability or versatility
If sensors have poor clock accuracy with ±15% deviation, then device compatibility is improved, but measurement precision deteriorates due to misalignment between sensor and processor clocks causing data loss or duplication
Solution Approach 1:
The patent changes the parameter of polling interval based on the clock accuracy characteristics of each sensor. Instead of using a fixed polling interval, the system adjusts the interval parameter dynamically according to the measured clock deviation. This allows the system to accommodate sensors with poor clock accuracy by using shorter intervals while maintaining compatibility with a wide range of sensors having different clock quality characteristics.
Solution Approach 2:
The patent performs preliminary characterization of each sensor's clock accuracy during initialization or calibration phases. This preliminary measurement of clock deviation is stored and used to pre-calculate optimal polling intervals before actual data collection begins. This preliminary action ensures that the system is prepared to handle the specific clock characteristics of each sensor, preventing data loss or duplication from the outset.
Data Source
AI summary
Aspects of the invention are related to a method for synchronizing a first sensor clock of a first sensor. The exemplary method comprises: correcting the first sensor clock for a first time, transferring data from the first sensor, and correcting the first sensor clock for a second time, wherein a time interval between two corrections of the first sensor clock is selected such that the first sensor clock is sufficiently aligned with a processor clock of a processor over the time interval.