Sensor Data Fusion Chiplet Architecture for Low-Latency Vehicle Computing
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Solution Overview
Problem
Current computer chips are limited in size due to transistor scaling limitations, leading to increased fragility and power consumption, and vehicle systems require multiple devices for complex functions, which are difficult to manage and costly.
Innovation Solution
An electronic circuit package utilizing chiplets for data fusion, where each chiplet performs a specific operation, allowing for parallel and series communication to enhance processing efficiency and reduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single complex computer chip is used to perform multiple operations, then device integration is improved, but chip size increases leading to increased fragility and manufacturing difficulty
Solution Approach 1:
The patent divides a complex computer chip into multiple smaller, independent chiplets that can be separately manufactured and then combined through interposers. Each chiplet performs a specific function, allowing for modular assembly that maintains functionality while reducing individual chip size and fragility issues.
Solution Approach 2:
The patent implements a hierarchical structure where multiple chiplets are nested on interposers, which themselves can be nested on substrates. This nested architecture allows complex functionality to be achieved through layered integration of smaller components, reducing the fragility of individual elements while maintaining overall system capability.
2Productivity
If transistor size is reduced to increase the number of transistors per chip, then computing performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
By segmenting the chip into multiple chiplets, each manufactured separately at optimal transistor densities, the patent avoids the need to manufacture an entire large chip at uniformly high precision. Each chiplet can be optimized for its specific function and manufactured at appropriate precision levels.
Solution Approach 2:
The patent allows different chiplets to have different manufacturing parameters, including transistor density and size, optimized for their specific functions. This enables high-performance computing capabilities without requiring all components to be manufactured at the same extreme precision level.
3Adaptability or versatility
If multiple separate computer devices are used for different vehicle functions, then functional capability is improved, but system complexity and management difficulty increase
Solution Approach 1:
The patent merges multiple separate computer devices into a single integrated electronic circuit package that contains multiple chiplets. This consolidation maintains the functional capabilities of separate devices while reducing system complexity through unified management of a modular architecture.
Solution Approach 2:
The electronic circuit package is designed with universal interposers and standardized interfaces that allow different chiplet types to be combined in various configurations. This multi-functional platform can accommodate different vehicle functions without requiring entirely separate device architectures.
4Device complexity
If a single large computer chip is used for all vehicle functions, then device count is reduced, but power consumption increases
Solution Approach 1:
By dividing the computing system into separate chiplets, each optimized for specific functions, the patent enables more efficient power utilization. Each chiplet can be activated only when its specific function is needed, avoiding the continuous power consumption of a monolithic chip that must support all functions simultaneously.
Solution Approach 2:
Different chiplets are designed with local optimizations for their specific functions, allowing each to operate at optimal efficiency for its task. This localized optimization reduces overall power consumption compared to a single chip that must accommodate all functions with uniform design compromises.
Data Source
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AI summary
An electronic circuit package for data fusion including a substrate, an interposer disposed on the substrate, and one or more first chiplets disposed on the interposer, the one or more first chiplets operable to carry out a first operation. The electronic circuit package including one or more memory chiplets disposed on the interposer, the one or more memory chiplets operable to store data. The electronic circuit package including one or more second chiplets disposed on the interposer, the one or more second chiplets operable to carry out a second operation.