Sensor Fusion Chiplet Architecture for Low-Latency Vehicle Computing
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Solution Overview
Problem
Current complex computer chips are limited by size and fragility, requiring multiple devices for vehicle functions, leading to inefficiency, high power consumption, and high manufacturing costs, which are unsuitable for next-gen vehicles.
Innovation Solution
An electronic circuit package utilizing chiplets for data fusion, where each chiplet is dedicated to a specific operation, allowing parallel or series communication to optimize processing and reduce latency, with universal plugs for easy upgrades and replacements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple separate computer devices are used for different vehicle functions, then functional versatility is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent divides a single computer device into multiple independent chiplets, each responsible for specific functions (e.g., sensor data processing, entertainment, driver assistance). This segmentation allows functional versatility while keeping each chiplet simple and manageable, resolving the contradiction between versatility and complexity.
Solution Approach 2:
The patent creates a universal computer device architecture where a single device can perform multiple functions through interchangeable chiplets. The standardized interface and modular design enable one device to replace multiple specialized devices, achieving versatility without increasing overall device complexity.
2Device complexity
If a single complex computer chip is used to consolidate multiple functions, then device complexity is reduced, but manufacturing yield and reliability worsen due to size
Solution Approach 1:
Instead of creating one large complex chip, the patent segments the functionality into multiple smaller chiplets. Each chiplet has fewer transistors and simpler circuitry, which improves manufacturing yield and reliability while maintaining the consolidated device complexity benefit.
Solution Approach 2:
The patent merges multiple simple chiplets into a single functional unit through standardized interfaces and interconnection technologies. This merging achieves the complexity reduction of a single device while preserving the reliability benefits of smaller, simpler components.
3Productivity
If transistor size is reduced to increase the number of transistors per chip, then computing power is improved, but chip size and fragility worsen
Solution Approach 1:
The patent segments the computing workload across multiple chiplets, each with a moderate number of transistors. This approach achieves high overall computing power without requiring each individual chip to be excessively large, thus avoiding increased fragility and weight.
Solution Approach 2:
The patent transitions from a two-dimensional planar chip layout to a three-dimensional stacked architecture with an interposer. This dimensional change allows multiple chiplets to be vertically integrated, increasing computing power density without proportionally increasing the physical footprint and fragility.
Data Source
AI summary
An electronic circuit package for data fusion including a substrate, an interposer disposed on the substrate, and one or more first chiplets disposed on the interposer, the one or more first chiplets operable to carry out a first operation. The electronic circuit package including one or more memory chiplets disposed on the interposer, the one or more memory chiplets operable to store data. The electronic circuit package including one or more second chiplets disposed on the interposer, the one or more second chiplets operable to carry out a second operation.