Sensor IC Disturb Immune Memory Fast Reset
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Solution Overview
Problem
Sensor integrated circuits face increased measurement latencies due to delays in digital logic circuits following supply voltage disturbances, leading to interrupted readings and prolonged reset times.
Innovation Solution
A sensor integrated circuit with a disturb immune memory and a main digital processor that performs fast or slow resets based on supply voltage levels, utilizing a fast reset circuit, slow reset circuit, and clock blanking circuit to quickly reload data and prevent clock signals during disturbances, thereby reducing reset time and maintaining operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a power on reset is triggered when supply voltage falls below minimum operating voltage, then the digital logic circuits are reset to normal operating conditions, but the reset time increases and measurement latency is prolonged
Solution Approach 1:
The disturb immune memory pre-stores filter coefficients and state machine states before voltage disturbances occur. When a disturbance happens, these pre-stored values are immediately loaded into the digital logic circuits, eliminating the need for time-consuming reset sequences and enabling instant recovery of normal operation
Solution Approach 2:
The system maintains backup copies of critical operational parameters (filter coefficients and state machine states) in the disturb immune memory, which serves as a protective cushion against voltage disturbances. This backup mechanism ensures that even if the main memory is corrupted during voltage fluctuations, the system can rapidly restore functionality using the protected backup data
2Stability of the object's composition
If digital logic circuits wait for delay period after power on reset, then they stabilize to normal operating conditions, but sensor readings are interrupted and measurement productivity decreases
Solution Approach 1:
Critical operational parameters are pre-calculated and stored in the disturb immune memory before voltage disturbances occur. This preliminary preparation allows the system to skip the stabilization delay period after reset, as the pre-stored values can be immediately loaded to restore circuit operation without waiting for gradual stabilization
Solution Approach 2:
The system skips the traditional delay period that follows power on reset by using pre-stored values from disturb immune memory. Instead of waiting for the digital logic circuits to gradually stabilize, the system rapidly loads the pre-prepared filter coefficients and state machine states, rushing through the recovery process and maintaining measurement productivity
Data Source
AI summary
A sensor integrated circuit includes a disturb immune memory configured to store data and a digital processor coupled to the disturb immune memory and including a main register. The digital processor is configured to perform one of a fast reset or slow reset of the main register according to a level of a supply voltage to the integrated circuit. The fast reset includes resetting the main register according to the data stored in the disturb immune memory and the slow reset includes resetting the main register according to a default state.