Sensor Output Formatting for High-Speed Fault-Tolerant Signaling

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Solution Overview

Problem

Existing sensor systems face challenges in efficiently communicating speed and direction information of a target object, particularly in high-speed scenarios and during diagnostic and critical fault conditions, where signal integrity and reliability are compromised.

Innovation Solution

An integrated circuit (IC) with a sensor that generates a formatted output signal, including speed and direction information, diagnostic flags, and signal integrity data, using a processor to monitor for faults and recover from critical failures, allowing for efficient communication of data bits and parity bits, even at high frequencies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of information

If traditional serial communication is used to send sensor data, then the communication protocol is simple, but the amount of data that can be transmitted is limited and signal integrity is compromised at high speeds

Engineering Contradiction:
Improvedata transmission completenessVSAvoidcommunication protocol complexity
Core Design Contradiction:
Loss of informationVSDevice complexity

Solution Approach 1:

The output signal is segmented into distinct components: speed/direction information, diagnostic flags, and parity bits. Each component is transmitted in a structured format within a single pulse train, allowing comprehensive data transmission while maintaining protocol simplicity through clear delimitation and timing windows for each data segment.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Multiple types of information (speed, direction, diagnostic faults, critical faults, and parity bits) are merged into a single integrated output signal transmitted via one pulse train. This consolidation eliminates the need for multiple separate communication channels while preserving all necessary data integrity information.

Inventive Principle:
Principle #5Merging (Combining)

2Productivity

If high-speed communication is implemented to improve productivity, then data transmission speed increases, but signal integrity and reliability deteriorate

Engineering Contradiction:
Improvedata transmission speedVSAvoidsignal integrity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

Parity bits are transmitted as part of the output signal to provide feedback on signal integrity. The system monitors for errors during high-speed transmission and can detect corruption, allowing for error correction or retransmission protocols that maintain reliability even at high communication speeds.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

Diagnostic flags are monitored and prepared in advance before transmission. Critical fault conditions are detected and flagged beforehand, allowing the system to preemptively handle potential signal integrity issues before they compromise data transmission reliability at high speeds.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If comprehensive diagnostic monitoring is added to detect all fault conditions, then system reliability improves, but device complexity increases

Engineering Contradiction:
Improvefault detection capabilityVSAvoidmonitoring system complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The processor performs multiple functions using the same diagnostic infrastructure: monitoring for diagnostic faults, detecting critical faults, generating appropriate flags, and transmitting all information through a unified pulse train format. This multi-functionality approach maintains high reliability while avoiding the complexity of separate dedicated circuits for each monitoring function.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10481218B2Providing information about a target object in a formatted output signal
Publication Date: 2019.11.19 ALLEGRO MICROSYSTEMS LLC
  • US10481218B2 patent drawing
  • US10481218B2 patent drawing
  • US10481218B2 patent drawing

AI summary

In one aspect, an integrated circuit (IC) includes a sensor. The sensor includes a processor configured to provide speed and/or direction of a target object based on the speed of the target object; monitor for a diagnostic fault; provide information if the diagnostic fault is detected; monitor for critical faults; and provide information if a critical fault is detected and the sensor recovers from the critical fault.