Integrated Sensor Package Air Gap Isolation
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Solution Overview
Problem
Modern electronic devices face challenges in integrating multiple sensors due to parasitic electrical effects from wire bonds and limited space, making it costly and inefficient to form multiple sensors on separate chip designs.
Innovation Solution
An integrated process flow is developed to form multiple sensors, including piezoelectric micromachined ultrasonic transducers (PMUT), pressure sensors, and accelerometers, on a common substrate using insulative layers as sacrificial and etch stop layers, and incorporating air gaps to reduce interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple sensors are formed on separate chip designs, then each sensor can be optimized independently, but the number of wire bonds increases causing parasitic electrical effects and increased cost
Solution Approach 1:
The patent combines multiple sensor types (accelerometer, pressure sensor, microphone) onto a single substrate, eliminating the need for multiple separate chips and wire bonds. This integration directly reduces parasitic electrical effects while maintaining independent sensor optimization through separate processing regions on the same chip.
2Productivity
If multiple sensors are integrated on a common substrate, then space usage is optimized and manufacturing steps are reduced, but parasitic electrical effects from close proximity may increase
Solution Approach 1:
The patent introduces air gaps as intermediary spaces between different sensor structures on the substrate. These air gaps act as electrical isolators that reduce parasitic coupling between adjacent sensors while maintaining compact integration, thus resolving the conflict between manufacturing efficiency and electrical interference.
3Ease of manufacture
If multiple sensors are integrated on a common substrate, then the number of manufacturing steps and costs are reduced, but sensor interference from close proximity may increase
Solution Approach 1:
Air gaps are introduced as intermediary spaces between different sensor structures on the substrate. These air gaps act as physical and acoustic isolators that reduce interference between adjacent sensors while maintaining compact integration, thus resolving the conflict between manufacturing efficiency and sensor interference.
4Reliability
If wire bonds are used to connect sensor chips to ASICs, then electrical connections are established, but parasitic capacitance and resistance increase
Solution Approach 1:
The patent integrates sensor elements and ASICs on the same substrate, eliminating the need for wire bonds between separate chips. This direct integration reduces parasitic capacitance and resistance by removing intermediate connection structures while maintaining reliable electrical connections through on-chip interconnects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the number of steps and costs associated with forming multiple sensors, minimizes parasitic electrical effects, and optimizes space usage, enabling more accurate and efficient signal output from integrated sensors.
Implementation Method 1
Some sensors utilize piezoelectric materials to convert strain of the piezoelectric material into electric signals
Implementation Method 2
air gaps between the two or more sensors mitigate interference due to the motion of the two or more structures
Data Source
AI summary
In some embodiments, the present disclosure relates to an integrated device, including: a substrate; a semiconductor layer on the substrate and including a first structure being one of a sound port, a sealed cavity, or a proof mass, and a second structure being one of the sound port, the sealed cavity, or the proof mass, where the second structure is a different one of the sound port, the sealed cavity, or the proof mass than the first structure; a piezoelectric layer on the semiconductor layer overlying the first structure and the second structure; and an air gap extending into the semiconductor layer from an upper surface of the piezoelectric layer, wherein the first structure and portions of the piezoelectric layer overlying the first structure are spaced from the second structure and portions of the piezoelectric layer overlying the second structure by the air gap.