Sensor Package Encapsulant Roughness for Precise TIV Alignment
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Solution Overview
Problem
The semiconductor industry faces manufacturing challenges in aligning and integrating sensing components within compact integrated fan-out packages, which affects the precision and efficiency of semiconductor package formation.
Innovation Solution
The solution involves forming alignment openings on dummy through insulator vias (TIVs) and using patterned dielectric layers to expose sensing components, allowing for precise alignment and integration of conductive patterns and dummy conductive patterns, which serve as alignment marks for subsequent patterning processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If sensing components are integrated into compact integrated fan-out packages, then integration density is improved, but alignment precision deteriorates
Solution Approach 1:
The patent introduces dummy through insulator vias (TIVs) as intermediary alignment marks. These dummy TIVs are formed in the encapsulant and serve as reference features for aligning the sensing components during packaging. The alignment marks bridge the gap between the compact package structure and the precise alignment requirement, enabling high integration density without sacrificing alignment precision.
2Manufacturing precision
If alignment openings are formed on dummy TIVs to improve alignment control, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The dummy through insulator vias serve multiple functions: they act as structural support elements within the encapsulant, provide alignment references for sensing component placement, and serve as markers for subsequent patterning processes. This multi-functionality reduces the need for separate alignment structures, thereby improving alignment control without proportionally increasing device complexity.
3Manufacturing precision
If patterned dielectric layers are used to expose sensing components, then alignment precision is improved, but manufacturing complexity increases
Solution Approach 1:
The alignment marks and dummy TIVs are formed in advance during the encapsulant formation process, before the sensing components are placed and before subsequent patterning operations. This preliminary preparation of alignment references enables precise alignment in later steps without adding complex real-time alignment mechanisms, thereby improving alignment precision while managing manufacturing complexity through process sequencing.
Data Source
AI summary
A semiconductor package includes a semiconductor die including a sensing component, an encapsulant laterally covering the semiconductor die, a through insulator via (TIV) and a dummy TIV penetrating through the encapsulant, a patterned dielectric layer disposed on the top surfaces of the encapsulant and the semiconductor die, a conductive pattern disposed on and inserted into the patterned dielectric layer to be in contact with the TIV and the semiconductor die, and a first dummy conductive pattern disposed on the patterned dielectric layer and connected to the dummy TIV. The top surface of the encapsulant is above and rougher than a top surface of the semiconductor die, and the sensing component is accessibly exposed by the patterned dielectric layer.