Sensor Shielding Reduces Capacitive Load
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Solution Overview
Problem
In indirect Time of Flight (ToF) distance measurement methods, the high-speed operation of transfer transistors leads to increased power consumption due to high capacitive loads on gate wiring lines, which is not effectively addressed by existing technologies.
Innovation Solution
A sensor device configuration with a laminated structure including a semiconductor substrate and a wiring layer part, where a shield part is formed around the gate wiring lines of transfer transistors to reduce capacitive load, utilizing a Low-k material and annular cross-sectional shape to minimize wiring capacitance, and potentially incorporating through vias to eliminate in-plane wiring, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If transfer transistors are driven at high speed to repeat on/off in a short cycle (10 MHz to 200 MHz) for indirect ToF distance measurement, then distance measurement precision is improved, but power consumption increases due to high capacitive load on gate wiring lines
Solution Approach 1:
A shield wiring line is introduced as an intermediary element between the gate wiring line and surrounding wiring lines. This shield wiring line acts as a mediator to block capacitive coupling from peripheral wiring lines, thereby reducing the capacitive load on the gate wiring line without affecting the high-speed switching function of the transfer transistors
Solution Approach 2:
The harmful capacitive load from peripheral wiring lines is extracted and isolated by introducing a dedicated shield wiring line. This separates the gate wiring line from the interfering electric fields of surrounding wiring, reducing the capacitive burden while maintaining the high-speed operation capability
2Use of energy by moving object
If a shield part is formed around the gate wiring line to reduce capacitive load, then power consumption is reduced, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The shield wiring line is positioned in a different wiring layer from the gate wiring line, utilizing the vertical dimension of the laminated structure. This three-dimensional arrangement allows the shield to effectively surround the gate wiring line in the thickness direction without adding in-plane complexity, as the shield can be formed in an adjacent layer and connected through via holes
3Use of energy by moving object
If the shield part covers a wide range in the thickness direction of the wiring layer part, then capacitive load reduction effect is enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The shield structure is segmented into manageable parts: the shield wiring line in one layer, via holes connecting to adjacent layers, and potential extension to multiple layers. This segmentation allows each component to be formed using standard semiconductor manufacturing processes with controlled precision requirements for each step, rather than requiring a single complex monolithic structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed configuration significantly reduces power consumption by minimizing wiring capacitance and enhancing manufacturing efficiency, while maintaining effective distance measurement capabilities using the indirect ToF method.
Implementation Method 1
the shield part can reduce the capacitive load on the gate wiring line from the peripheral wiring lines
Implementation Method 2
a photoelectric conversion element that performs photoelectric conversion
Data Source
AI summary
A sensor device according to the present technology includes: a semiconductor substrate; and a wiring layer part formed on the semiconductor substrate and having a plurality of wiring layers, in which a pixel is disposed in a laminated structure of the semiconductor substrate and the wiring layer part, the pixel including a photoelectric conversion element that performs photoelectric conversion, a first charge holding part and a second charge holding part that hold charges accumulated in the photoelectric conversion element, a first transfer transistor that transfers the charges to the first charge holding part, and a second transfer transistor that transfers the charges to the second charge holding part, and a shield part is disposed to surround each gate wiring line of each of the first and second transfer transistors extending in a thickness direction in the wiring layer part.