Sensor-Mounted Wafer Structure for Warp-Free Plasma Sensing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional Sensor On Wafer (SOW) technology faces issues such as sensor warpage due to temperature rise, reduced durability, and chamber contamination from exposed sensing probes, as well as misidentification of plasma sensor wafers as two separate wafers due to thickness and exposed sensing probes.
Innovation Solution
The design includes a sensor-mounted wafer with a lower case and upper case having different thicknesses, featuring mounting grooves and insertion grooves of varying depths to ensure close contact between electronic components and improved durability, and a sensing probe that senses plasma without exposure, using capacitance between probe pads to avoid contamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional SOW mounts sensors and electronic components in cavities at the same depth, then the structure is simple to manufacture, but durability is deteriorated and warpage occurs when temperature rises
Solution Approach 1:
The patent applies local quality by forming cavities at different depths within the wafer substrate corresponding to the different heights of electronic components. Each cavity is precisely positioned and depth-adjusted to accommodate specific components, ensuring optimal contact and thermal management while maintaining manufacturing feasibility through localized processing.
2Reliability
If wafer thickness is increased to 1200 μm or more, then durability is improved, but the wafer is misidentified as two separate wafers
Solution Approach 1:
The patent resolves the identification issue by transitioning from a two-dimensional planar view to a three-dimensional structural view. The through-type cavity penetrating the entire wafer thickness serves as a unique dimensional feature that confirms single-wafer status despite increased thickness, allowing equipment to distinguish the monolithic structure from stacked wafers.
3Measurement precision
If sensing probe is directly exposed to sense plasma density, then sensing capability is achieved, but chamber interior is contaminated
Solution Approach 1:
The patent extracts the sensing function from the exposed probe configuration and relocates it to an embedded sensor within the wafer substrate. The sensor is positioned to detect plasma parameters through the wafer thickness without physical exposure, separating the sensing capability from the contamination source while maintaining measurement functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances durability by preventing warpage and reduces chamber contamination while accurately identifying the wafer as a single unit, maintaining high plasma sensing accuracy without exposing the probe, thus improving semiconductor manufacturing yield.
Implementation Method 1
an adhesive layer placed between the mounting groove and the plurality of insertion grooves
Implementation Method 2
sensing probe including a pair of probe pads placed in the mounting groove, and being connected to the plasma sensor through wiring formed on the circuit board
Data Source
AI summary
The present invention provides a sensor mounted wafer, including: a lower case in which a mounting groove is formed; a circuit board on which a plurality of electronic components having different heights are mounted, and placed in the mounting groove; an upper case in which a plurality of insertion grooves having different depths are formed, and bonded together to the lower case so that the plurality of electronic components are inserted into the plurality of insertion grooves; and an adhesive layer placed between the mounting groove and the plurality of insertion grooves, in which the insertion grooves are formed to have different depths according to the heights of the plurality of the electronic components.


