Multi-Core Sensor Evaluation with Watchdog Controller
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Solution Overview
Problem
Existing sensor arrangements for safety applications require complex and resource-intensive redundant structures to meet safety norms, particularly due to cyclical processor testing and redundant hardware, which increases design effort and hardware requirements.
Innovation Solution
A sensor arrangement utilizing a multi-core processor with redundant signal evaluation and a watchdog controller for monitoring, where the multi-core processor does not need a fail-safe structure, and the watchdog controller ensures error detection and system safety without additional processors, achieving a structurally simple safety structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two independent processors are used for redundant evaluation, then safety level is improved, but device complexity increases
Solution Approach 1:
The patent merges the safety monitoring function into a centralized watchdog controller that supervises a single multi-core processor, rather than using two independent processors. The watchdog controller implements safety checks and monitors the processor states, combining redundancy management into one dedicated component while allowing the main processor to handle all evaluation tasks.
Solution Approach 2:
The watchdog controller acts as an intermediary between the multi-core processor and the safety requirements. It monitors processor functionality, detects errors, and ensures safety compliance without requiring the complex dual-processor architecture. The watchdog serves as a mediator that enables safety with simpler processor configuration.
2Reliability
If two independent processors are used for redundant evaluation, then safety level is improved, but hardware footprint increases
Solution Approach 1:
The patent combines the functions of multiple processors into a single multi-core processor unit that is supervised by a watchdog controller. This consolidation reduces the hardware footprint by eliminating duplicate CPU and memory units while maintaining safety through centralized monitoring and error detection capabilities.
3Reliability
If cyclical processor testing is implemented, then safety level is improved, but device complexity increases
Solution Approach 1:
The watchdog controller autonomously performs cyclical testing and monitoring of the multi-core processor without requiring complex external testing infrastructure. It independently checks processor functionality, detects errors, and manages safety compliance, enabling self-service safety verification with minimal design effort.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces design complexity and hardware effort while meeting safety requirements by using a multi-core processor with redundant signal evaluation and a watchdog controller for error monitoring, ensuring reliable operation and safety without the need for additional processors.
Implementation Method 1
a transmitter unit which emits light beams
Implementation Method 2
a receiver unit which receives light beams
Data Source
Figure 1
Figure 2~3
AI summary
The invention relates to a sensor arrangement (100) with a ribbon-shaped position measurement system which has an arrangement of position markers (10) in which the positions of the position markers (10) within the position measurement system (2) are encoded as position values. The sensor arrangement (100) further comprises an optical sensor (1) movable relative to the position measurement system (2), wherein the optical sensor (1) has a light-beam emitting transmitter unit (9), a light-beam receiving receiver unit (9), and an evaluation unit (7) for evaluating received signals from the receiver unit. By reading position markers (10) using the optical sensor (1), its position relative to the position measurement system (2) can be determined.The evaluation unit (7) comprises a multi-core processor (16) with at least two processing cores (17a, 17b), wherein the received signals from the receiver unit are fed to the processing cores (17a, 17b) via two channels and evaluated redundantly there. The evaluation unit (7) includes a watchdog controller (18) by means of which the functions of the multi-core processor (16) are monitored.