SeOI Chip Fabrication With Selective Channel Thinning
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing manufacturing processes for semiconductor-on-insulator integrated circuit chips are complex and costly due to the need for sequential processes to fabricate devices with different thicknesses, leading to potential damage of the top Si-containing layer and high complexity.
Innovation Solution
A method involving a semiconductor-on-insulator structure with a buried insulating layer, where field effect transistors are built with different preliminary gate lengths, followed by selective removal and thinning of the top semiconductor layer to achieve specific thicknesses for high and low voltage devices, simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If classical dopant implantation is used to elaborate wells regions under source and drain electrodes of PD devices, then PD devices can be fabricated, but the top Si-containing layer and buried oxide are damaged
Solution Approach 1:
The patent applies local quality by creating different thickness regions of the top Si-containing layer: thinner regions (e.g., 5-20 nm) for FD devices and thicker regions (e.g., 50-100 nm) for PD devices. This allows each device type to have optimized electrical characteristics while using the same fabrication process sequence, avoiding the need for damaging dopant implantation in thin regions.
Solution Approach 2:
The patent performs preliminary thinning of the top Si-containing layer to different thicknesses before device fabrication. By pre-establishing the appropriate thickness distribution across the substrate, the method enables subsequent FD and PD device fabrication without requiring damaging dopant implantation steps, thus preserving layer integrity while achieving device performance.
2Reliability
If sequential manufacturing processes are used to elaborate thick layer-based devices first and then thin layer-based devices, then high performance devices can be fabricated, but manufacturing complexity and costs increase
Solution Approach 1:
The patent merges the fabrication of FD and PD devices into a single unified process sequence. By simultaneously preparing both device types on the same substrate with different local thicknesses of the top layer, the method eliminates the need for separate sequential manufacturing processes, thereby reducing manufacturing complexity and costs while maintaining high device performance.
Solution Approach 2:
The patent creates a universal fabrication process that can produce both FD and PD devices using the same sequence of processing steps. The method employs a single top Si-containing layer that serves multiple functions: acting as the active layer for FD devices in thinner regions and as the source/drain extension layer for PD devices in thicker regions, thus achieving multi-functionality without process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables high-performance, low-leakage devices with reduced manufacturing complexity and cost by co-integrating high and low voltage devices on a thin top semiconductor layer, improving reliability and performance.
Implementation Method 1
a source region and a drain region formed by n-type or p-type dopant implantation in the top semiconductor-containing layer
Data Source
AI summary
A method for manufacturing a semiconductor-on-insulator (SeOI) chip comprises: a) providing a SeOI structure, b) building a plurality of isolated field effect transistors (FET) each comprising: —a preliminary gate above a channel region, the FETs from a first group having a first preliminary gate length and the FETs from a second group having a smaller second preliminary gate length, —a source region and a drain region, and —a source electrode and a drain electrode, c) removing at least the preliminary gates of the FETs from the second group, leaving access to channel regions of the FETs, d) thinning a top layer in channel regions of the FETs from the second group, the top layer in channel regions of the first group of FETs having a different thickness, and e) forming functional gates simultaneously on channel regions of the FETs whose preliminary gates were removed.