SeOI Data-Path Cell With Back Gate Control
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Solution Overview
Problem
Miniaturization in semiconductor devices leads to performance issues such as short channel effects, small channel volume effects, and fabrication irregularities, necessitating data-path cells with improved performance and size characteristics.
Innovation Solution
Data-path cells are designed on a semiconductor-on-insulator substrate with an array of field-effect transistors, featuring a back gate control region that modifies performance based on bias voltage, reducing capacitance and increasing conductance, thereby optimizing footprint and performance for specific integrated circuit environments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If miniaturization is applied to reduce device size, then footprint is reduced, but performance deteriorates due to short channel effects and small channel volume effects
Solution Approach 1:
The patent introduces a back gate control region formed in the bulk substrate beneath the insulating layer, adding a vertical control dimension to the transistor structure. This allows performance optimization through back gate bias without increasing the planar footprint, effectively resolving the contradiction between miniaturization and performance maintenance.
Solution Approach 2:
The patent modifies transistor performance by changing the electrical parameter (bias voltage) applied to the back gate control region. By adjusting the back gate bias, the invention optimizes transistor characteristics such as threshold voltage and channel conductivity, thereby improving performance without increasing device area.
2Ease of manufacture
If standard cells are used for simple functions, then design cost is reduced, but performance characteristics are insufficient for high-speed circuits
Solution Approach 1:
The patent segments the gate control function into two independent parts: a front gate for basic control and a back gate for performance optimization. This segmentation allows the use of standard cell structures while adding specialized control capability, thereby achieving high-speed performance without completely redesigning the cell from scratch.
Solution Approach 2:
The back gate control region provides multi-functionality by enabling both performance optimization for high-speed operation and compatibility with standard cell architectures. The same transistor structure can be used across different circuits, with the back gate bias adjusted to meet specific performance requirements, thus reducing design cost while achieving high speed.
3Reliability
If data-path cells are specifically adapted for particular circuit environments, then performance characteristics are improved, but design cost increases
Solution Approach 1:
The patent introduces dynamically adjustable back gate bias that can be modified based on circuit operating conditions. This dynamic control allows a single standardized cell design to adapt to different circuit environments and performance requirements, eliminating the need for multiple specialized cell designs and thereby reducing design cost while maintaining optimized performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves a 20% increase in operating speed, 20% reduction in power consumption, and 20% decrease in footprint, with up to 33% reduction in capacitance and one decade reduction in inactive mode power consumption, while maintaining conductance, thus addressing miniaturization challenges.
Implementation Method 1
Each transistor comprises: in the thin layer of semiconductor material, a source region, a drain region and a channel region interposed between the source and drain regions, above the channel region, a front gate control region; and one or more back gate control regions formed in the bulk substrate beneath the channel region of one or more FETs. The back gate control region associated with a particular transistor is configured and positioned so that the performance characteristics of that transistor varies in dependence on a bias applied to the back gate control region.
Data Source
AI summary
The invention provides a data-path cell specifically adapted to its environment for use in an integrated circuit produced on a semiconductor-on-insulator (SeOI) substrate. The data-path cell includes an array of field-effect transistors, each transistor having a source region, a drain region and a channel region formed in the thin semiconductor layer of the SeOI substrate, and further having a front gate control region formed above the channel region. In particular, one or more transistors of the data-path cell further includes a back gate control region formed in the bulk substrate beneath the channel region and configured so as to modify the performance characteristics of the transistor in dependence on its state of bias. Also, an integrated circuit including one or more of the data-path cells and methods for designing or driving these data-path cells.