SeOI Transistor Gate Using Single Crystal Silicon
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to achieve low sheet and contact resistivity in drain and source regions while maintaining channel controllability in densely packed field-effect transistors, particularly due to the limitations of conventional gate dielectric thickness and the polysilicon-oxide interface, which leads to poor adhesion and reliability issues.
Innovation Solution
The use of a semiconductor-on-insulator (SeOI) structure with a single crystal silicon layer as the gate electrode and a buried oxide layer as the gate dielectric, forming a superior single crystal silicon-oxide interface that eliminates grain boundaries and inhomogeneous dopant profiles, enhancing the reliability and performance of transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the gate dielectric thickness is reduced to increase capacitive coupling and improve switching speed, then the switching speed is improved, but leakage currents exponentially increase
Solution Approach 1:
The patent employs a composite gate dielectric structure consisting of multiple layers with different dielectric materials (e.g., silicon oxide, silicon nitride, or high-k materials like hafnium oxide). This composite structure allows optimization of the overall dielectric properties to achieve high capacitive coupling for fast switching while maintaining sufficient thickness to prevent excessive leakage currents.
Solution Approach 2:
The patent changes the dielectric parameters by introducing materials with different dielectric constants and thicknesses in a stacked configuration. By adjusting the combination of materials and their respective thicknesses, the system achieves the desired capacitive coupling strength without requiring an excessively thin single-layer dielectric, thus avoiding the exponential increase in leakage current.
2Ease of manufacture
If polysilicon is used for the gate electrode, then the manufacturing is simplified, but the interface with gate dielectric shows grain boundaries causing poor adhesion and reliability failures
Solution Approach 1:
The patent introduces an intermediary layer or modifies the interface structure between the gate electrode and gate dielectric to eliminate the direct polysilicon-dielectric interface that causes grain boundary issues. This may involve using a different gate electrode material (such as single-crystal silicon, metal, or metal alloy) that forms a grain-boundary-free interface with the dielectric, thereby maintaining ease of manufacture while significantly improving interface adhesion and reliability.
3Quantity of substance
If transistor dimensions are reduced to increase packing density, then the packing density is improved, but channel controllability and sheet resistivity become difficult to maintain
Solution Approach 1:
The patent uses composite gate dielectric structures with high-k materials that provide higher capacitive coupling per unit thickness. This allows for effective channel control in scaled-down transistors without requiring proportionally smaller dielectric thicknesses, thereby maintaining channel controllability even as transistor dimensions are reduced to increase packing density.
Data Source
AI summary
The present invention relates to a semiconductor device that has a semiconductor-on-insulator (SeOI) structure, which includes a substrate, an insulating layer such as an oxide layer on the substrate and a semiconductor layer on the insulating layer with a field-effect-transistor (FET) formed in the SeOI structure from the substrate and deposited layers, wherein the FET has a channel region in the substrate, a gate dielectric layer that is made from at least a part of the oxide layer of the SeOI structure; and a gate electrode that is formed at least partially from a part of the semiconductor layer of the SeOI structure. The invention further relates to a method of forming one or more field-effect-transistors or metal-oxide-semiconductor transistors from a semiconductor-on-insulator structure that involves patterning and etching the SeOI structure, forming shallow trench isolations, depositing insulating, metal or semiconductor layers, and removing mask and/or pattern layers.