Separate Alias Queues for Store Data and Address Dependency Prediction
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Solution Overview
Problem
Out-of-order processors experience memory violations and load misses due to the out-of-order execution of load and store instructions, where the store instruction modifies data affecting subsequent load operations, leading to instruction replay and memory violations, which existing solutions fail to accurately predict and prevent effectively.
Innovation Solution
A processor circuit with a first and second alias queue module and a pattern detection module that records and matches next sequential instruction pointer values for store data and store address instructions to determine dependencies, ensuring that load instructions are executed after their corresponding store instructions, thereby reducing load misses and memory violations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If out-of-order execution is used to improve processor performance, then execution speed is improved, but memory violations and load misses occur due to incorrect execution order
Solution Approach 1:
The patent applies preliminary action by recording the program order of load and store instructions in advance using alias queue modules before out-of-order execution occurs. The system captures the original sequential execution order and uses it to guide the reordering process, ensuring that load instructions only execute after their dependent store instructions have completed, thus preventing memory violations while maintaining performance benefits
Solution Approach 2:
The patent implements feedback through a pattern detection module that continuously monitors executed instructions and updates dependency patterns. When a load instruction executes, the system checks against recorded patterns to determine if any pending store instructions should block its execution. This feedback loop ensures correct memory access ordering while allowing maximum out-of-order execution, resolving the contradiction between speed and reliability
2Measurement precision
If alias queue modules record Nsip values for both StD and StA instructions separately, then prediction accuracy is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the alias queue into separate modules: one dedicated to recording store data (StD) instruction patterns and another for store address (StA) instruction patterns. Each module independently tracks Nsip values for its specific instruction type, allowing the system to accurately distinguish between data dependencies and address dependencies. This segmentation improves prediction accuracy by preventing confusion between different dependency types while keeping each module's structure simple and manageable
Data Source
AI summary
A processor circuit and an operation method thereof are provided. The processor circuit includes a first alias queue module, a second alias queue module, and a pattern detection module. The pattern detection module is coupled to the first alias queue module and the second alias queue module. When a next sequential instruction pointer value of a store data instruction of the first alias queue module is matched, and a next sequential instruction pointer value of a store address instruction of the second alias queue module is matched, the pattern detection module determines that the load instruction depends on the store data instruction or the store address instruction according to a pattern value corresponding to the store data instruction.