Separate Clock Synchronous Architecture for PCIe Systems
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Solution Overview
Problem
Conventional PCIe systems face challenges in building large systems due to high costs associated with distributing high-frequency signals synchronously, particularly due to issues with clock skew, power consumption, and routing complexities in common clock architectures.
Innovation Solution
Implementing a separate clock synchronous architecture that uses a low-frequency beacon to synchronize independently clocked devices, allowing each device to generate a local high-frequency clock, thereby eliminating the need for distributing high-speed clocks and simplifying system design and clock routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a common clock architecture is used to distribute high-frequency signals synchronously, then system synchronization is achieved, but system cost and complexity increase significantly
Solution Approach 1:
The patent divides the system into independently clocked devices, each with its own local clock generator. Instead of distributing a single common clock signal throughout the system, each device generates and maintains its own clock independently, eliminating the complex clock distribution network while achieving synchronization through beacon signal coordination.
Solution Approach 2:
The patent introduces a low-frequency beacon signal as an intermediary mechanism. This beacon serves as a mediator that allows independently clocked devices to synchronize their operations without requiring direct high-frequency clock distribution. The beacon acts as a common reference that coordinates the independent clock sources.
2Reliability
If high-frequency clock signals are distributed throughout the system, then synchronous operation is maintained, but power consumption increases
Solution Approach 1:
The system segments the clocking function so that each device generates its own clock locally rather than receiving it from a central source. This eliminates the power consumption associated with distributing high-frequency clock signals through extensive routing infrastructure, while maintaining synchronous operation through coordinated beacon signals.
Solution Approach 2:
The patent extracts the high-frequency clock generation function from the central clock distribution system and places it locally at each device. By taking out the clock generation function from the distribution network, the system eliminates the power consumption of the distribution infrastructure while preserving synchronous operation.
3Reliability
If conventional PCIe clocking constraints are applied, then signal integrity is maintained, but system scalability is limited
Solution Approach 1:
The patent changes the frequency parameter of the synchronization signal from high-frequency to low-frequency. By using low-frequency beacon signals instead of high-frequency clock signals for distribution, the system maintains signal integrity over longer distances and through more complex routing, enabling larger-scale systems while individual devices continue to operate at high frequencies for performance.
Data Source
AI summary
An apparatus includes a plurality of independently clocked devices and a low frequency beacon. Each of the plurality of independently clocked devices has a respective local clock generator. The low frequency beacon communicates a low frequency synchronization signal to each of the independently clocked devices. The respective local clock generators of the plurality of independently clocked devices are generally synchronized using the low frequency synchronization signal.