Separate Code and System Buses for Computing Device
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Solution Overview
Problem
Computing devices experience bottlenecks and delays when transceiving information via a single bus, leading to performance issues due to data path bottlenecks and memory location delays.
Innovation Solution
The implementation of a computing device configuration that utilizes separate buses for instruction and data information, where the host device receives instruction information via a code bus and data via a system bus, allowing for efficient transceiving and reducing bottlenecks by optimizing bus usage based on address maps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If information is transceived via a single bus, then device complexity is reduced, but bottlenecks and delays occur in data path and memory location
Solution Approach 1:
The patent divides the single bus into multiple separate buses (code bus for instruction information and system bus for data information). This segmentation allows independent transmission paths for different types of information, eliminating bottlenecks and delays that occur when all information shares a single bus, thereby improving information transceiving efficiency without significantly increasing overall system complexity.
2Productivity
If separate buses are used for instruction and data information, then information transceiving efficiency is improved, but device complexity increases
Solution Approach 1:
The patent implements address maps (code address map and data address map) that can be selectively activated based on the type of information being transceived. The system bus and code bus can serve multiple functions: the system bus handles both data transmission and can be configured for instruction transmission when needed, while the code bus specifically handles instruction information. This multi-functionality allows efficient use of bus resources while managing device complexity.
3Productivity
If multiple buses are used for information transceiving, then bottlenecks are prevented and delays are reduced, but bus resource management becomes more complex
Solution Approach 1:
The patent implements an automatic bus selection mechanism where the system determines which bus (code bus or system bus) to use based on the address map configuration and the type of information being transceived. This self-service approach eliminates the need for manual bus resource management, allowing the system to automatically route instruction information through the code bus and data information through the system bus, thereby preventing bottlenecks while simplifying operation.
Data Source
AI summary
A computing device includes a host device and a storage device. The host device is configured to receive instruction information via a code bus based on a code address comprised in a code address map of particular address maps and receive data via a system bus that is separate from the code bus based on a data address included in a data address map. The storage device is configured to store target instruction information via the system bus and provide the target instruction information to the host device via the code bus in response to a request from the host device for an object code address included in the code address map and corresponding to the target instruction information.