Separate-Die Network-on-Chip for FPGA Fabric Bandwidth

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Solution Overview

Problem

In programmable logic devices, incorporating a Network on Chip (NOC) within the fabric die disrupts the fabric and reduces performance due to limited space, increased connectivity, and bandwidth issues, making it difficult to facilitate data communication between sectors across different fabric dies.

Innovation Solution

Embedding the NOC on a separate die with fabric support circuitry allows for data communication between sectors, resolving bandwidth issues and enabling design relocations, security isolation, and faster configuration by providing alternate communication pathways and increasing connectivity without affecting the fabric's performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If NOC is incorporated within the fabric die, then data communication between sectors is enabled, but fabric performance is reduced due to limited space and increased connectivity requirements

Engineering Contradiction:

Improvedata communication capabilityVSAvoidfabric performance

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent divides the system into two separate dies: one dedicated to programmable logic fabric and another to NOC circuitry. This segmentation allows each component to be optimized independently, with the fabric die focusing on computational performance and the NOC die providing dedicated communication infrastructure, thereby resolving the space and performance conflict.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent transitions from a two-dimensional integration approach (embedding NOC within the same fabric die) to a three-dimensional stacked architecture where NOC is implemented on a separate die in a vertical arrangement. This dimensional change enables high-bandwidth communication without consuming fabric die space, maintaining fabric performance while enabling sector-to-sector data communication.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Productivity

If NOC is embedded on a separate die, then bandwidth is enhanced and fabric performance is maintained, but device complexity increases

Engineering Contradiction:

ImprovebandwidthVSAvoidmulti-dimensional die system

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent combines multiple functions into the NOC die, including sector-to-sector communication, memory interface, and configuration pathways. By merging these communication and control functions onto the dedicated NOC die, the system achieves high bandwidth without proportionally increasing overall complexity, as the fabric die remains focused on its primary computational role.

Inventive Principle:

Principle #5Merging (Combining)

3Reliability

If NOC is separated from fabric, then security isolation and fast reconfiguration are enabled, but connectivity requirements increase

Engineering Contradiction:

Improvesecurity isolationVSAvoidconnectivity requirements

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces a dedicated interface layer between the fabric die and NOC die that acts as an intermediary for all communication. This interface includes configurable routing logic and protocol handling that enables security isolation by controlling access paths, while simultaneously managing connectivity requirements through standardized interface protocols that simplify the complexity of inter-die communication.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS11296706B2Embedded network on chip accessible to programmable logic fabric of programmable logic device in multi-dimensional die systems

Publication Date: 2022.04.05 ALTERA CORP

AI summary

An integrated circuit device may include programmable logic fabric disposed on a first integrated circuit die, such that the programmable logic fabric may include a first region of programmable logic fabric and a second region of programmable logic fabric. The first region of programmable logic fabric is configured to be programmed with a circuit design that operates on a first set of data. The integrated circuit may also include network on chip (NOC) circuitry disposed on a second integrated circuit die, such that the NOC circuitry is configured to communicate data between the first integrated circuit die and the second integrated circuit die.