Separate Drain-Side Dummy Word Lines to Reduce Program Disturb
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Solution Overview
Problem
In 3D stacked non-volatile memory devices, disturbs during programming and read operations, particularly affecting drain-side data memory cells, lead to increased threshold voltage and potential read errors due to channel gradient issues.
Innovation Solution
The implementation of separate dummy word line layers that can be driven with different voltages to optimize the channel gradient, reducing the likelihood of disturbs on drain-side data memory cells by setting optimal voltages based on programming or read operations, temperature, and error counts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If dummy word line layers are shared among all sub-blocks, then device complexity is reduced, but program disturb on drain-side data memory cells increases due to inability to optimize voltage settings for different sub-blocks
Solution Approach 1:
The dummy word line layers are segmented into separate portions for different sub-blocks. Specifically, the first dummy word line layer is divided into first portions corresponding to first sub-blocks and second portions corresponding to second sub-blocks, allowing independent voltage control for each sub-block group while maintaining structural organization
Solution Approach 2:
Different voltage settings are applied to dummy word line portions based on their local sub-block requirements. The control circuitry selectively applies first voltage settings to first dummy word line portions and second voltage settings to second dummy word line portions, optimizing local conditions for each sub-block to minimize program disturb
2Productivity
If higher voltages are applied during programming to improve write speed, then productivity increases, but channel voltage gradients increase causing more electron-hole pair generation and read errors
Solution Approach 1:
Dummy word line layers are activated with appropriate voltages before and during programming operations to preemptively counteract the formation of harmful channel voltage gradients. This preliminary action suppresses electron-hole pair generation at the drain-side of memory strings before programming occurs, preventing program disturb while allowing high programming voltages to be applied for fast writing
Data Source
AI summary
Disturbs are reduced during programming and read operations for drain-side memory cells in a string by controlling dummy word line portions separately in selected and unselected sub-blocks. One or more of the dummy word line layers are separated so that they can be driven with different voltages. This allows the channel gradient to be optimized to reduce the likelihood of disturbs. In another aspect, a stack of alternating conductive and dielectric layers is formed in two parts, with lower pillars which comprise select gate transistors, source-side dummy memory cells and data memory cells, below upper pillars which comprise drain-side dummy memory cells and select gate transistors. The upper pillars are relatively narrow to provide a more compact structure. Moreover, the centerline of some upper pillars can be offset from the centerline of corresponding lower pillars to provide room for an isolation region.